W199H 데이터 시트보기 (PDF) - Cypress Semiconductor
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W199H Datasheet PDF : 14 Pages
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PRELIMINARY
W199
SDRAM Clock Outputs, SDRAM, SDRAM0:11 (Lump Capacitance Test Load = 30 pF) (continued)
PCI Clock Outputs, PCI_F and PCI1:5 (Lump Capacitance Test Load = 30 pF)
Parameter
Description
Test Condition/Comments
tP
Period
Measured on rising edge at 1.5V
tH
High Time
Duration of clock cycle above 2.4V
tL
Low Time
Duration of clock cycle below 0.4V
tR
Output Rise Edge Rate Measured from 0.4V to 2.4V
tF
Output Fall Edge Rate Measured from 2.4V to 0.4V
tD
Duty Cycle
Measured on rising and falling edge at 1.5V
tJC
Jitter, Cycle-to-Cycle
Measured on rising edge at 1.5V. Maximum
difference of cycle time between two adja-
cent cycles.
tSK
Output Skew
Measured on rising edge at 1.5V
tO
CPU to PCI Clock Skew Covers all CPU/PCI outputs. Measured on
rising edge at 1.5V. CPU leads PCI output.
fST
Frequency Stabilization Assumes full supply voltage reached within
from Power-up (cold start) 1 ms from power-up. Short cycles exist pri-
or to frequency stabilization.
Zo
AC Output Impedance Average value during switching transition.
Used for determining series termination
value.
Min.
30
12.0
12.0
1
1
45
1.5
Typ.
30
Max.
4
4
55
250
500
4
3
Unit
ns
ns
ns
V/ns
V/ns
%
ps
ps
ns
ms
Ω
IOAPIC Clock Output (Lump Capacitance Test Load = 20 pF)
Parameter
f
tR
tF
tD
fST
Zo
Description
Test Condition/Comments
Frequency, Actual
Frequency generated by crystal oscillator
Output Rise Edge Rate Measured from 0.4V to 2.0V
Output Fall Edge Rate Measured from 2.0V to 0.4V
Duty Cycle
Measured on rising and falling edge at 1.25V
Frequency Stabilization Assumes full supply voltage reached within
from Power-up (cold start) 1 ms from power-up. Short cycles exist prior
to frequency stabilization.
AC Output Impedance
Average value during switching transition.
Used for determining series termination value.
CPU = 66.6/100 MHz
Min. Typ. Max.
14.31818
1
4
1
4
45
55
1.5
15
Unit
MHz
V/ns
V/ns
%
ms
Ω
11
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