U631H256 데이터 시트보기 (PDF) - Zentrum Mikroelektronik Dresden AG
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U631H256 Datasheet PDF : 12 Pages
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U631H256
SRAM operation cannot commence until tRESTORE after
VCC exceeds VSWITCH.
If the U631H256 is in a WRITE state at the end of
power up RECALL, the SRAM data will be corrupted.
To help avoid this situation, a 10 kΩ resistor should be
connected between W and VCC.
HARDWARE PROTECTION
The U631H256 offers hardware protection against
inadvertent STORE operation through VCC sense.
For VCC < VSWITCH the software initiated STORE opera-
tion will be inhibited.
LOW AVERAGE ACTIVE POWER
The U631H256 has been designed to draw significantly
less power when E is LOW (chip enabled) but the
access cycle time is longer than 55 ns.
When E is HIGH the chip consumes only standby cur-
rent.
The overall average current drawn by the part depends
on the following items:
1. CMOS or TTL input levels
2. the time during which the chip is disabled (E HIGH)
3. the cycle time for accesses (E LOW)
4. the ratio of READs to WRITEs
5. the operating temperature
6. the VCC level
December 12, 1997
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