W184 데이터 시트보기 (PDF) - Cypress Semiconductor

부품명

상세내역

일치하는 목록

W184

Six Output Peak Reducing EMI Solution

Cypress Semiconductor 

W184

Application Information

Recommended Circuit Configuration

For optimum performance in system applications the power

supply decoupling scheme shown in Figure 4 should be used.

VDD decoupling is important to both reduce phase jitter and

EMI radiation. The 0.1-µF decoupling capacitor should be

placed as close to the VDD pin as possible, otherwise the in-

creased trace inductance will negate its decoupling capability.

The 10-µF decoupling capacitor shown should be a tantalum

type. For further EMI protection, the VDD connection can be

made via a ferrite bead, as shown.

Clock Output

R1

1

Logic Input

2

Reference Input 3

XTAL connection or NC

4

5

Logic Input 6

Logic Input 7

R1

8

Clock Output

9

R1

10

Clock Output

R1

11

Clock Output

12

C1

0.1 µF

24 Logic Input

23 Logic Input

22 Logic Input

21

20

19 NC

18 Logic Input

17

16

R1

15

14

R1

13

R1

C1

0.1 µF

Clock Output

Clock Output

Clock Output

C1

0.1 µF

C1

0.1 µF

FB

3.3 or 5V System Supply

C2

10-µF Tantalum

Figure 4. Recommended Circuit Configuration

Ordering Information

Ordering Code

Package

Name

W184

H

W184-5

Package Type

24-Pin SSOP (209-mil)

Document #: 38-00797-B

7

Share Link: