73K324BL-IH 데이터 시트보기 (PDF) - TDK Corporation
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73K324BL-IH Datasheet PDF : 26 Pages
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73K222BL
V.22, V.21, Bell 212A, Bell 103
Single-Chip Modem with Integrated Hybrid
DYNAMIC CHARACTERISTICS AND TIMING (continued)
PARAMETER
CONDITION
MIN
GUARD TONE GENERATOR
Tone Accuracy
550 Hz
1800 Hz
-20
Tone Level
550 Hz
-4.0
(Below DPSK Output)
1800 Hz
-7.0
Harmonic Distortion
700 to 2900 Hz
550 Hz
1800 Hz
TIMING (Refer to Timing Diagrams)
TAL
CS/Address setup before ALE Low
12
TLA
CS CS hold after ALE low
0
NOM
-3.0
-6.0
MAX
+20
-2.0
-5.0
-50
-60
UNIT
Hz
dB
dB
dB
dB
ns
ns
TLC
TCL
TRD
TLL
TRDF
TRW
TWW
TDW
TWD
ADD Address hold after ALE Low
10
ALE Low to RD/WR Low
10
RD/WR Control to ALE High
0
Data out from RD Low
0
ALE width
15
Data float after RD High
RD width
50
WR width
50
Data setup before WR High
15
Data hold after WR High
12
ns
ns
ns
70
ns
ns
50
ns
ns
ns
ns
ns
TCKD
Data out after EXCLK Low
200
ns
TCKW (serial mode)
WR after EXCLK Low
150
ns
TDCK (serial mode)
Data setup before EXCLK Low
150
ns
TAC (serial mode)
Address setup before control*
50
ns
TCA (serial mode)
Address hold after control*
50
ns
TWH (serial mode)
Data Hold after EXCLK
20
* Control for setup is the falling edge of RD or WR. Control for hold is the falling edge of RD or the rising edge
of WR.
NOTE: Asserting ALE, CS, and RD or WR concurrently can cause unintentional register accesses. When using
non-8031 compatible processors, care must be taken to prevent this from occurring when designing the
interface logic.
19
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