SAA5355 데이터 시트보기 (PDF) - Philips Electronics
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SAA5355 Datasheet PDF : 31 Pages
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Philips Semiconductors
Single-chip colour CRT controller
(FTFROM)
Product specification
SAA5355
APPLICATION INFORMATION
More detailed application information is available on request
BASIC VIDEOTEX DECODER CONFIGURATION
A basic, practical decoder configuration is shown in Fig.14, reference should also be made to the block diagram Fig.1.
Fig.14 Basic videotex decoder configuration.
Character and attribute data is fetched from the external memory, processed by the row buffer fill logic according to the
stack coding scheme (in stack mode) and then fed into one half of the dual display row buffer. The data fetch process
takes place during one line-flyback period (per row) and, since time is required to complete the fill, the other half of the
dual row buffer is used for display. The row buffers exchange functions on alternate rows each holds the 40 columns
of 32 bits required to define explicitly every character in a row.
The addresser is used for row buffer filling and for fetching screen colours, and during the display time it is also used for
addressing DRCS characters.
Timing
The timing chain operates from an external 6,041957 MHz clock or an on-chip fixed-frequency crystal oscillator.
The basic video format is 40 characters per row, 20/21 rows per page and 10 video lines per row. FTFROM will also
operate with 25 rows per page and 9 video lines per row.
The display is generated to the normal 525-line/59,94 Hz scanning standard (interlaced or non-interlaced). In addition to
composite sync (pin 32) for conventional timebases, a clock output at approximately 1 MHz or 6 MHz (pin 29) is
available for driving other devices, and a clock output (pin 27) is available for hard-copy dot synchronization.
A defined-display-area timing signal (pin 33) simplifies the application of external peripherals such as a light pen;
this signal is nominally coincident with the character dot information.
March 1986
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