LP61L1024 데이터 시트보기 (PDF) - AMIC Technology

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LP61L1024

128K X 8 BIT 3.3V HIGH SPEED LOW VCC CMOS SRAM

AMIC Technology 

AC Test Conditions

Input Pulse Levels

Input Rise and Fall Time

Input and Output Timing Reference Levels

Output Load

0V to 3.0V

3 ns

1.5V

See Figures 1 and 2

LP61L1024

+3.3V

320Ω

I/O

350Ω

30pF*

* Including scope and jig.

+3.3V

320Ω

I/O

350Ω

5pF*

* Including scope and jig.

Figure 1. Output Load

Data Retention Characteristics (TA = 0°C to 70°C)

Symbol

Parameter

Min.

VDR1

2

VCC for Data Retention

VDR2

2

ICCDR1

-

Data Retention Current

ICCDR2

-

tCDR

Chip Disable to Data Retention Time

0

tR

Operation Recovery Time

5

Figure 2. Output Load for tCLZ1,

tCLZ2, tOHZ, tOLZ, tCHZ1,

tCHZ2, tWHZ, and tOW

Max.

3.6

3.6

5

5

-

-

Unit

Conditions

CE1 ≥ VCC - 0.2V

V

CE2 ≥ VCC - 0.2V or

CE2 ≤ 0.2V

CE2 ≤ 0.2V

V

CE1 ≥ VCC - 0.2V or

CE1 ≤ 0.2V

VCC = 3.0V

CE1 ≥ VCC - 0.2V

mA

CE2 ≥ VCC - 0.2V

VIN ≥ VCC - 0.2V or

VIN ≤ 0.2V

VCC = 3.0V

CE2 ≤ 0.2V

mA

CE1 ≤ 0.2V

VIN ≥ VCC - 0.2V or

VIN ≤ 0.2V

ns

See Retention Waveform

ms

(August, 2002, Version 2.1)

10

AMIC Technology, Inc.

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