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MT9044

T1/E1/OC3 System Synchronizer

Mitel Networks 

Advance Information

MT9044

In Normal Mode, the DCO provides an output signal

which is frequency and phase locked to the selected

input reference signal.

In Holdover Mode, the DCO is free running at a

frequency equal to the last (less 30ms to 60ms)

frequency the DCO was generating while in Normal

Mode.

In Freerun Mode, the DCO is free running with an

accuracy equal to the accuracy of the OSCi 20MHz

source.

Output Interface Circuit

The output of the DCO (DPLL) is used by the Output

Interface Circuit to provide the output signals shown

in Figure 5. The Output Interface Circuit uses four

Tapped Delay Lines followed by a T1 Divider Circuit ,

an E1 Divider Circuit, a DS2 Divider Circuit and an

analog PLL to generate the required output signals.

Four tapped delay lines are used to generate a

16.384MHz, 12.352MHz, 12.624MHz and 19.44 MHz

signals.

The E1 Divider Circuit uses the 16.384MHz signal to

generate four clock outputs and three frame pulse

outputs. The C8o, C4o and C2o clocks are

generated by simply dividing the C16o clock by two,

four and eight respectively. These outputs have a

nominal 50% duty cycle.

The T1 Divider Circuit uses the 12.384MHz signal to

generate two clock outputs. C1.5o and C3o are

generated by dividing the internal C12 clock by four

and eight respectively. These outputs have a

nominal 50% duty cycle.

The DS2 Divider Circuit uses the 12.624 MHz signal

to generate the clock output C6o. This output has a

nominal 50% duty cycle.

Tapped

Delay

Line

T1 Divider

12MHz

C1.5o

C3o

From

DPLL

Tapped

Delay

Line

E1 Divider

16MHz

Tapped

Delay

Line

12MHz DS2 Divider

C2o

C4o

C8o

C16o

F0o

F8o

F16o

C6o

Tapped

Delay

Line

19MHz

C19o

ACKi

Analog PLL

ACKo

Figure 5 - Output Interface Circuit Block

Diagram

The frame pulse outputs (F0o, F8o, F16o, TSP, RSP)

are generated directly from the C16 clock.

The T1 and E1 signals are generated from a

common DPLL signal. Consequently, the clock

outputs C1.5o, C3o, C2o, C4o, C8o, C16o, F0o, F16o

and C6o are locked to one another for all operating

states, and are also locked to the selected input

reference in Normal Mode. See Figures 20 and 21.

All frame pulse and clock outputs have limited driving

capability, and should be buffered when driving high

capacitance (e.g. 30pF) loads.

Analog Phase Lock Loop (APLL)

The analog PLL is intended to be used to achieve a

50% duty cycle output clock. Connecting C19o to

ACKi will generate a phase locked 19.44 MHz ACKo

output with a nominal 50% duty cycle. The analog

PLL has an intrinsic jitter of less than 0.01 U.I. In

order to achieve this low jitter level a separate pin is

provided to power (AVdd) the analog PLL.

7

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