MK50H27 데이터 시트보기 (PDF) - STMicroelectronics

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MK50H27

Signalling System 7 Link Controller

STMicroelectronics 

MK50H27

T3

T4n

T4e

T5

T6

T7

TP

RESERVED/ 16-bit Scaler

ALIGNED TIMEOUT TIMER PERIOD. T3 determines the maximum

time the MK50H27 will wait in the ALIGNED state before signalling link

failure. Represented as two’s complement.

NORMAL PROVING PERIOD. T4n determines the length of the

normal proving period as defined in CCITT Q.703. Represented as

two’s complement.

EMERGENCY PROVING PERIOD. T4e determines the length of the

emergency proving period as defined in CCITT Q.703. Represented

as two’s complement.

BUSY TRANSMIT PERIOD. T5 determines the amount of time

the MK50H27 will wait between transmissions of status indication "B"

while in congestion state. Represented as two’s complement.

EXCESSIVE BUSY TIMER PERIOD. T6 determines the amount of

time the MK50H27 will allow a remote site to remain in the congested

state before signalling link failure. Represented as two’s complement.

EXCESSIVE ACKNOWLEDGE TIMER PERIOD. T7 determines the

maximum amount of time the MK50H27 will wait for an expected

acknowledgement of an MSU before signalling link failure. Repre-

sented as two’s complement.

TRANSMIT POLLING PERIOD. This scaled timer determines the

length of time between transmit signal unit checks. Unless TDMD

(see CSR0) is set or a signal unit is received on the link, no at-

tempt to transmit a signal unit in the transmit descriptor ring is made

until TP expires. At TP expiration all transmit signal units in the

transmit descriptor ring are sent. Represented as two’s complement.

Can be programmed as all zeroes for compatibliity with existing MK50H27

applications. However, if ESEN=1 (CSR2<14>), then this field is de-

fined as a 16-bit scaler for all of the timers, and it will be used instead

of the Scaler at IADR+02. This prescaler is incremented once every

32 system clock pulses. When it reaches zero the timers are incre-

mented and the prescaler is reset. This field is interpreted as the

two’s complement of the prescaler period. This 16-bit scaler is NOT

multiplied by 16 when read into the MK50H27.

Timers For Optional TTC JT-Q703 Compliance

Tf

FISU Sending Interval timer. This timer, located at IADR + 144 will

determine the amount of time between transmission of FISUs when in

TTC JT-Q703 compliant mode (CSR2<08> JSS7E=1). Represented as

two’s complement.

Ts

SIOS Sending Interval timer. This timer, located at IADR + 146 will

determine the amount of time between transmission of SIOS signal

units when in TTC JT-Q703 compliant mode (CSR2<08> JSS7E=1).

Represented as two’s complement.

To

SIO Sending Interval timer. This timer, located at IADR + 148 will

determine the amount of time between transmission of SIOsignal units

when in TTC JT-Q703 compliant mode (CSR2<08> JSS7E=1). Repre-

sented as two’s complement.

Ta

SIE Sending Interval timer. This timer, located at IADR + 150 will

determine the amount of time between transmission of SIE signal units

when in TTC JT-Q703 compliant mode (CSR2<08> JSS7E=1). Repre-

sented as two’s complement.

Note: The Tf, Ts, To, & Ta timers are only active and valid when JSS7E=1 (CSR2<08>).

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