MK50H27 데이터 시트보기 (PDF) - STMicroelectronics

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MK50H27

Signalling System 7 Link Controller

STMicroelectronics 

MK50H27

4.1.2.1 Control and Status Register 0 (CSR0)

BIT NAME

12 DRX

11 TXON

10 RXON

09 INEA

08 INTR

07 MERR

06 MISS

05 ROR

DESCRIPTION

Disable the Receiver prevents the MK50H27 from further access to

the Receiver Descriptor Ring. No received signal units are accepted

after finishing reception of any signal unit in reception at the time

of DRX being set. RXON acknowledges changes to DRX, see be-

low. DRX is READ/WRITE.

TRANSMITTER ON indicates that the transmit ring access is enabled.

TXON is set as the Power On primitive is issued if the DTX bit is "0"

or afterward as DTX is cleared. TXON is cleared upon recognition of

DTX being set, by sending a Power Off primitive in CSR1, or by a

Bus RESET. If TXON is clear, the host may modify the Transmit

Descriptor Ring entries regardless of the state of the OWNA bits.

TXON is READ ONLY; writing to this bit has no effect.

RECEIVER ON indicates that the receive ring access is enabled.

RXON is set as the Power On primitive is issued if DRX=0, or after-

ward as DRX is cleared. RXON is cleared upon recognition of DRX

being set, by sending a Power Off primitive in CSR1, or by a

Bus RESET. RXON is READ ONLY; writing to this bit has no effect.

INTERRUPT ENABLE allows the INTR I/O pin to be driven low when

the Interrupt Flag is set. If INEA = 1 and INTR = 1 the INTR I/O pin will

be low. If INEA = 0 the INTR I/O pin will be high, regardless of the

state of the Interrupt Flag. INEA is READ/WRITE set by writing a

"1" into this bit and is cleared by writing a "0" into this bit, by Bus RE-

SET, or while in the Power Off phase. INEA may not be set while in

the Power Off phase.

INTERRUPT FLAG indicates that one or more of the following interrupt

causing conditions has occurred: MISS, MERR, RINT, TINT, PINT. If

INEA = 1 and INTR = 1 the INTR I/O pin will be low. INTR is READ

ONLY, writing this bit has no effect. INTR is cleared as the specific

interrupting condition bits are cleared. INTR is also cleared by Bus

RESET or by issuing a Power Off primitive.

MEMORY ERROR is set when the MK50H27 is the Bus Master and

READY has not been asserted within 256 SYSCLKs (25.6 usec @

10MHz) after asserting the address on theDAL lines. When a Mem-

ory Error is detected, the MK50H27 releases the bus, the receiver

and transmitter are turned off, and an interrupt is generated if INEA =

1. MERR is READ/CLEAR ONLY and is set by the chip and cleared by

writing a "1" into the bit. Writing a "0" has no effect. It is cleared by

Bus RESET or by issuing a Power Off primitive.

MISSED MSU is set when the receiver loses a MSU because it does

not own a receive buffer indicating loss of data. When MISS is set, an

interrupt will be generated if INEA = 1. MISS is READ/CLEAR ONLY

and is set by MK50H27 and cleared by writing a "1" into the bit. Writ-

ing a "0" has no effect. It is also cleared by Bus RESET or by issu-

ing a Power Off primitive.

RECEIVER OVERRUN indicates that the Receiver FIFO was full When

the receiver was ready to input data to the Receiver FIFO. The sig-

nal unit being received is lost but is recoverable according to the Link

Level protocol. When ROR is set, an interrupt is generated if INEA =

1. ROR is READ/CLEAR ONLY and is set by MK50H27 and cleared

by writing a "1" into the bit. Writing a "0" has no effect. It is also

cleared by Bus RESET or by issuing a Power Off primitive.

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