EBS12UC6APS-80 데이터 시트보기 (PDF) - Elpida Memory, Inc
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EBS12UC6APS-80 Datasheet PDF : 14 Pages
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EBS12UC6APS
Byte No. Function described
28
Row active to row active min
(-7A/7AL, -75/75L)
(-80/80L)
29
/RAS to /CAS delay min
(-7A/7AL)
(-75/75L, -80/80L)
30
Minimum /RAS pulse width
(-7A/7AL, -75/75L)
(-80/80L)
31
Density of each bank on module
Address and command signal input
32
setup time
(-7A/7AL, -75/75L)
(-80/80L)
Address and command signal input
33
hold time
(-7A/7AL, -75/75L)
(-80/80L)
34
Data signal input setup time
(-7A/7AL, -75/75L)
(-80/80L)
35
Data signal input hold time
(-7A/7AL, -75/75L)
(-80/80L)
36 to 61 Superset information
62
SPD data revision code
63
Checksum for Bytes 0 to 62
(-7A/7AL)
(-75/75L)
(-80/80L)
64
Manufacturer’s JEDEC ID code
65 to 71 Manufacturer’s JEDEC ID code
72
Manufacturing location
73 to 90 Manufacturer’s part number
91 to 92 Revision code
93 to 94 Manufacturing date
95 to 98 Assembly serial number
99 to 125 Manufacturer specific data
126
Reserved (Intel specification
frequency)
127
Reserved (Intel specification /CAS#
latency support)
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value
0 0 0 0 1 1 1 1 0FH
0 0 0 1 0 0 0 0 10H
0 0 0 0 1 1 1 1 0FH
0 0 0 1 0 1 0 0 14H
0 0 1 0 1 1 0 1 2DH
0 0 1 1 0 0 0 0 30H
0 0 1 0 0 0 0 0 20H
0 0 0 1 0 1 0 1 15H
0 0 1 0 0 0 0 0 20H
0 0 0 0 1 0 0 0 08H
0 0 0 1 0 0 0 0 10H
0 0 0 1 0 1 0 1 15H
0 0 1 0 0 0 0 0 20H
0 0 0 0 1 0 0 0 08H
0 0 0 1 0 0 0 0 10H
0 0 0 0 0 0 0 0 00H
0 0 0 1 0 0 1 0 12H
0 1 1 1 1 0 0 0 78H
1 0 1 1 1 0 0 1 B9H
1 1 1 1 1 0 1 0 FAH
1 1 1 1 1 1 1 0 FEH
0 0 0 0 0 0 0 0 00H
0 1 1 0 0 1 0 0 64H
1 1 0 0 0 1 1 1 C7H
Comments
15ns
16ns
15ns
20ns
45ns
48ns
128MB
1.5ns
2ns
0.8ns
1ns
1.5ns
2ns
0.8ns
1ns
1.2
Elpida Memory
100MHz
Data Sheet E0224E20 (Ver. 2.0)
5
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