M41T80M 데이터 시트보기 (PDF) - STMicroelectronics

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M41T80M

Serial access real-time clock with alarm

STMicroelectronics 

Operation

M41T80

Table 2.

Sym

AC characteristics

Parameter(1)

Min Typ Max Units

fSCL

SCL clock frequency

0

tLOW

Clock low period

1.3

tHIGH

Clock high period

600

tR

SDA and SCL rise time

tF

SDA and SCL fall time

START condition hold time

tHD:STA

(after this period the first clock pulse is generated)

600

START condition setup time

tSU:STA

(only relevant for a repeated start condition)

600

tSU:DAT(2) Data setup time

100

tHD:DAT Data hold time

0

tSU:STO STOP condition setup time

600

Time the bus must be free before a new

tBUF

transmission can start

1.3

400 kHz

µs

ns

300 ns

300 ns

ns

ns

ns

µs

ns

µs

1. Valid for ambient operating temperature: TA = –40 to 85 °C; VCC = 2.0 to 5.5 V (except where

noted).

2. Transmitter must internally provide a hold time to bridge the undefined region (300 ns max) of

the falling edge of SCL.

2.2

Note:

READ mode

In this mode the master reads the M41T80 slave after setting the slave address (Figure 8:

READ mode sequence). Following the WRITE mode control bit (R/W=0) and the

acknowledge bit, the word address 'An' is written to the on-chip address pointer. Next the

START condition and slave address are repeated followed by the READ mode control bit

(R/W=1). At this point the master transmitter becomes the master receiver. The data byte

which was addressed will be transmitted and the master receiver will send an acknowledge

bit to the slave transmitter. The address pointer is only incremented on reception of an

acknowledge clock. The M41T80 slave transmitter will now place the data byte at address

An+1 on the bus, the master receiver reads and acknowledges the new byte and the

address pointer is incremented to “An+2.”

This cycle of reading consecutive addresses will continue until the master receiver sends a

STOP condition to the slave transmitter.

The system-to-user transfer of clock data will be halted whenever the address being read is

a clock address (00h to 07h). The update will resume due to a stop condition or when the

pointer increments to any non-clock address (08h-13h).

This is true both in READ mode and WRITE mode.

An alternate READ mode may also be implemented whereby the master reads the M41T80

slave without first writing to the (volatile) address pointer. The first address that is read is the

last one stored in the pointer (see Figure 9: Alternative READ mode sequence).

10/27

Doc ID 9074 Rev 5

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