EDL1216CASA 데이터 시트보기 (PDF) - Elpida Memory, Inc
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EDL1216CASA Datasheet PDF : 59 Pages
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EDL1216CASA
DC Characteristics 1 (TA = –25 to +85°C, VDD, VDDQ = 1.8V ± 0.15V, VSS, VSSQ = 0V)
Parameter
/CAS latency
Operating current
(CL = 2)
(CL = 3)
Standby current in power down
Standby current in power down
(input signal stable)
Symbol
IDD1
IDD1
IDD2P
IDD2PS
Standby current in non power
down
IDD2N
Standby current in non power
down (input signal stable)
Active standby current in power
down
Active standby current in power
down (input signal stable)
IDD2NS
IDD3P
IDD3PS
Active standby current in non
power down
IDD3N
Active standby current in non
power down (input signal stable)
IDD3NS
Burst operating current
(CL = 2)
IDD4
(CL = 3)
IDD4
Refresh current
(CL = 2)
IDD5
(CL = 3)
IDD5
Self refresh current
PASR="000" (Full)
IDD6
PASR="001" (2BK)
PASR="010" (1BK)
PASR="101" (1/2 BK)
PASR="110" (1/4 BK)
PASR="000" (Full)
IDD6
PASR="001" (2BK)
PASR="010" (1BK)
PASR="101" (1/2 BK)
PASR="110" (1/4 BK)
PASR="000" (Full)
IDD6
PASR="001" (2BK)
PASR="010" (1BK)
PASR="101" (1/2 BK)
PASR="110" (1/4 BK)
Standby current in deep power
down mode
IDD7
Grade max.
60
60
0.9
0.5
5.5
2
1.5
1
17
12
40
60
130
130
0.35
0.25
0.18
0.12
0.09
0.20
0.15
0.10
0.08
0.07
0.60
0.50
0.43
0.37
0.34
10
Unit
Test condition
Notes
mA
Burst length = 1
1
tRC ≥ tRC min., IO = 0mA,
mA
One bank active
mA
CKE ≤ VIL max., tCK = 15ns
mA
CKE ≤ VIL max., tCK = ∞
CKE ≥ VIH min., tCK = 15ns,
mA
/CS ≥ VIH min.,
Input signals are changed one
time during 30ns.
mA
CKE ≥ VIH min., tCK = ∞,
Input signals are stable.
mA
CKE ≤ VIL max., tCK = 15ns
mA
CKE ≤ VIL max., tCK = ∞
CKE ≥ VIH min., tCK = 15 ns,
mA
/CS ≥ VIH min.,
Input signals are changed one
time during 30ns.
mA
CKE ≥ VIH min., tCK = ∞,
Input signals are stable.
mA
tCK ≥ tCK min.,
IOUT = 0mA, All banks active
2
mA
mA
tRC ≥ tRC min.
3
mA
mA
TCSR="00" (Ts*4 ≤ 70°C)
mA
CKE ≤ 0.2V
mA
mA
mA
mA
TCSR="01" (Ts*4 ≤ 45°C)
mA
CKE ≤ 0.2V
mA
mA
mA
mA
TCSR="11" (Ts*4 ≤ 85°C)
mA
CKE ≤ 0.2V
mA
mA
mA
µA
CKE ≤ 0.2V
Data Sheet E0195E30 (Ver. 3.0)
5
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