YTD423 데이터 시트보기 (PDF) - Yamaha Corporation

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YTD423

ISDN BRI controller with B-ch HDLC controllers

Yamaha Corporation 

4. HDLC controller for B-channels

 HDLC frame control (Flag control, optional marks or ags in idle state, optional FCS generation/checking,

automatic zero insertion/deletion, abort pattern transmission/detection, optional address eld genera-

tion/checking etc.)

 Full-duplex communication 2 2 channels

 Data rates Network synchronization clock mode : 56 k or 64 kbps

Network independent clock mode : Up to 128 kbps

 Optional 16-bit/32-bit CRC

 Programmable data transfer modes

{ DMA transfer mode (with the built-in DMA controller)

3 optional 8-bit/16-bit access

3 24-bit address

3 4 channels

{ I/O transfer mode (with the built-in FIFO)

3 Tx FIFO : 32 bytes 2 2

3 Rx FIFO : 64 bytes 2 2

3 Variable interrupt levels

3 Byte/Word access selection

 Optional transparent mode (disable HDLC controller function)

5. Low-power operation (the host processor clock control function, LSI internal clock freezing function)

6. CMOS technology

7. 100-pin SQFP

8. Single +5V volt supply

1.2 Applications

 Terminal Adapter (TA)

 Router

 ISDN PC Card

 PBX

 ISDN Telephone

3

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