PRELIMINARY
Timing Diagrams (continued)
Pipeline Timing
CLK
tCH
tCYC
tAS
ADD A
B
C
D
tADS
ADSP
tADH
CY7C1345
tCL
E
F
G
H
ADSC
ADV
CE1
tCES
tCEH
CE
WE
OE
tWES
ADSP ignored
with CE1 HIGH
tWEH
tCLZ
Data
In/Out
tCDV
Q(A) Q(B) Q(C) Q(D)
Device originally
deselected
D (E) D (F) D (G) DD((CH))
tDOH
tCHZ
WE is the combination of BWE, BWS[1:0], and GW to define a write cycle (see Write Cycle Definition table).
CE is the combination of CE2 and CE3. All chip selects need to be active in order to select
the device. RAx stands for Read Address X, WAx stands for Write Address X, Dx stands for Data-in X,
Qx stands for Data-out X.
= DON’T CARE
= UNDEFINED
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