STA001 데이터 시트보기 (PDF) - STMicroelectronics
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STA001 Datasheet PDF : 20 Pages
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STA001
Table 2. First data byte selection table (selection of synthesizer channel) using a 14.725Mhz quartz
MSB
LSB
RF LO freq. selected
Units
Division ratio
selected on
synthesizer
Notes
D6 D5 D4 D3 D2 D1 D0
from REF1 to
LO1
0
0 0 0 11
0 1325.25 +6*0.46015625 MHz
(1328.010938)
360.75
Lowest
selectable
freq.
0
0 0 0 11
1 1325.25 +7*0.46015625 MHz
360.875
0
0 0 1 00
0 1325.25+ 8*0.46015625 MHz
361
-
-
-
-
--
-
0
0 1 1 10
0
1338.134375
MHz
363.5
first used freq.
-
-
-
-
--
-
1325.25+
MHz 360 + N*0.125 general freq.
N*0.46015625
generation
N=(D6..D0) represented
rule
decimal number
1
1 0 1 10
1
1375.407031
MHz
373.625 Last used freq.
-
-
-
-
--
-
1
1 1 1 11
0
1383.229688
MHz
375.75
1
1 1 1 11
1
1383.689844
MHz
375.875
-
-
-
-
--
-
0
0 0 0 10
1
1325.25
+133*0.46015625
(1386.450781)
MHz
376.625
Highest
selectable
freq.
1
0 0 0 10
1
1357.000781
MHz
368.625
Startup
presetted data
Table 3. Second data byte selection table (LOCK test on both pll, dividers test and IF pll test)
MSB
LSB
D6 D5 D4 D3 D2 D1 D0
Working mode
Notes
0
0
0
0
0
0
0
Lock test on RF pll
lock flag to be tested: TLCK;
Startup presetted data
0
0
0
0
1
0
0
Lock test on IF pll
lock flag to be tested: TLCK
0
0
0
0
0
0
1 Lock test on RF and IF pll lock flag to be tested: TLCK
0
0
1
0
0
1
0
First pll programmable
output freq. divided by 16
divider test
available on TLCK
0
0
1
1
0
1
0 First pll reference divider
output freq. divided by 8
test
available on TLCK
0
0
1
0
1
1
0 Second pll fixed divider
output freq. divided by 2
test
available on TLCK
0
0
1
1
1
1
0
Second pll reference output freq. available on TLCK
divider test
1
0
0
0
0
0
0 Test frequency on IF pll Division ratio changed to 987
divider by 1034
1
1
0
0
0
0
0 Test frequency on IF pll Division ratio changed to 1081
divider by 1034
15/20
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