IS62LV12816ALL-70B 데이터 시트보기 (PDF) - Integrated Silicon Solution

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IS62LV12816ALL-70B

128K x 16 CMOS STATIC RAM

Integrated Silicon Solution 

IS62LV12816ALL

ISSI ®

AC WAVEFORMS

WRITE CYCLE NO. 1(1,2) (CS Controlled, OE = HIGH or LOW)

1

t WC

ADDRESS

VALID ADDRESS

2

t SA

t SCS

t HA

CS

t AW

3

t PWE1

WE

t PWE2

t PBW

4

UB, LB

t HZWE

t LZWE

5

DOUT

DATA UNDEFINED

HIGH-Z

t SD

t HD

6

DIN

DATAIN VALID

UB_CSWR1.eps

7

Notes:

1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CS and WE inputs and at least

one of the LB and UB inputs being in the LOW state.

2. WRITE = (CS) [ (LB) = (UB) ] (WE).

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11

12

Integrated Silicon Solution, Inc. — 1-800-379-4774

7

Rev. A

04/17/01

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