CDP1823CDX 데이터 시트보기 (PDF) - Intersil

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CDP1823CDX

128-Word x 8-Bit LSI Static RAM

Intersil 

CDP1823, CDP1823C

Dynamic Electrical Specifications At TA = -40 to +85oC, VDD ±5%, tR, tF = 20ns, CL = 100pF

LIMITS

CDP1823

CDP1823C

PARAMETER

VDD (NOTE 2) (NOTE 1)

(NOTE 2) (NOTE 1)

SYMBOL (V)

MIN

TYP

MAX

MIN

TYP

Read Cycle (See Figure 1)

Access Time From Address

tAA

5

Change

10

-

275

450

-

275

-

150

250

-

-

Access Time From Chip

Select

tDOA

5

10

-

150

250

-

150

-

100

150

-

-

MRD to Output Active

tAM

5

10

-

150

250

-

150

-

100

150

-

-

Data Hold Time After Read

tDOH

5

25

50

75

25

50

10

15

25

40

-

-

NOTES:

1. Typical values are at TA = 25oC and nominal voltage.

2. Time required by a limit device to allow for the indicated function.

+

tAA

MAX

450

-

250

-

250

-

75

-

ADDRESS

UNITS

ns

ns

ns

ns

ns

ns

ns

ns

tAM

MRD

CS2, CS3, CS5

CS1, CS4

DATA OUT

HIGH IMPEDANCE

tDOA

VALID DATA

tDOH

90%

10%

NOTE:

1. MWR is high during read operation. Timing measurement reference is 0.5 VDD.

FIGURE 1. READ CYCLE TIMING DIAGRAM

6-27

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