HB52RF1289E2-75B 데이터 시트보기 (PDF) - Elpida Memory, Inc

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HB52RF1289E2-75B

1 GB Registered SDRAM DIMM 128-Mword × 72-bit, 133 MHz Memory Bus, 2-Bank Module (36 pcs of 64 M × 4 Components) PC133 SDRAM

Elpida Memory, Inc 

HB52RF1289E2-75B

Byte No. Function described

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments

20

SDRAM device attributes:

0 0 0 0 0 0 0 1 01

0

W latency

21

SDRAM device attributes

0 0 0 1 1 1 1 1 1F

Registered

22

SDRAM device attributes:

General

0 0 0 0 1 1 1 0 0E

VCC ± 10%

23

SDRAM cycle time

(2nd highest CE latency)

10 ns

1 0 1 0 0 0 0 0 A0

CL = 2

*5

24

SDRAM access from Clock

0 1 1 0 0 0 0 0 60

*5

(2nd highest CE latency)

6 ns

25

SDRAM cycle time

(3rd highest CE latency)

Undefined

0 0 0 0 0 0 0 0 00

26

SDRAM access from Clock (3rd 0 0 0 0 0 0 0 0 00

highest CE latency)

Undefined

27

Minimum row precharge time 0 0 0 1 0 1 0 0 14

20 ns

28

Row active to row active min 0 0 0 0 1 1 1 1 0F

15 ns

29

RE to CE delay min

0 0 0 1 0 1 0 0 14

20 ns

30

Minimum RE pulse width

0 0 1 0 1 1 0 1 2D

45 ns

31

Density of each bank on module 1 0 0 0 0 0 0 0 80

2 bank

512M byte

32

Address and command signal 0 0 0 1 0 1 0 1 15

input setup time

1.5 ns*5

33

Address and command signal 0 0 0 0 1 0 0 0 08

input hold time

0.8 ns*5

34

Data signal input setup time

0 0 0 1 0 1 0 1 15

1.5 ns*5

35

Data signal input hold time

0 0 0 0 1 0 0 0 08

0.8 ns*5

36 to 61 Superset information

0 0 0 0 0 0 0 0 00

Future use

62

SPD data revision code

0 0 0 0 0 0 1 0 02

JEDEC2

63

Checksum for bytes 0 to 62

1 0 1 0 1 1 0 1 AD

173

64

Manufacturer’s JEDEC ID code 0 0 0 0 0 1 1 1 07

HITACHI

65 to 71 Manufacturer’s JEDEC ID code 0 0 0 0 0 0 0 0 00

72

Manufacturing location

× × × × × × × × ××

*2 (ASCII-

8bit code)

Data Sheet E0018H10

6

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