HB52RF1289E2 데이터 시트보기 (PDF) - Elpida Memory, Inc

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HB52RF1289E2

1 GB Registered SDRAM DIMM 128-Mword × 72-bit, 133 MHz Memory Bus, 2-Bank Module (36 pcs of 64 M × 4 Components) PC133 SDRAM

Elpida Memory, Inc 

HB52RF1289E2-75B

Relationship Between Frequency and Minimum Latency

HB52RF1289E2-75B

Parameter

133

100

Frequency (MHz)

CE latency CE latency

=4

=3

tCK (ns)

PC100

Symbol Symbol 7.5

10

Active command to column command (same bank) IRCD

3

2

Active command to active command (same bank) IRC

9

7

Notes

1

= [IRAS + IRP]

1

Active command to precharge command (same bank) IRAS

6

5

1

Precharge command to active command (same bank) IRP

3

2

1

Write recovery or data-in to precharge command

I DPL

Tdpl 1

1

1

(same bank)

Active command to active command (different bank) IRRD

2

2

1

Self refresh exit time

I SREX

Tsrx 2

2

2

Last data in to active command

(Auto precharge, same bank)

I APW

Tdal 4

3

= [IDPL + IRP]

Self refresh exit to command input

I SEC

9

7

= [IRC]

3

Precharge command to high impedance

Last data out to active command

(auto precharge) (same bank)

I HZP

Troh 4

3

I APR

0

0

Last data out to precharge (early precharge)

I EP

–3

–2

Column command to column command

I CCD

Tccd 1

1

Write command to data in latency

I WCD

Tdwd 1

1

DQMB to data in

I DID

Tdqm 1

1

DQMB to data out

I DOD

Tdqz 3

3

CKE to CK disable

I CLE

Tcke 2

2

Register set to active command

I RSA

Tmrd 1

1

S to command disable

I CDD

0

0

Power down exit to command input

I PEC

1

1

Notes: 1. IRCD to IRRD are recommended value.

2. Be valid [DESL] or [NOP] at next command of self refresh exit.

3. Except [DESL] and [NOP]

Data Sheet E0018H10

13

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