HB52RF1289E2-75B 데이터 시트보기 (PDF) - Elpida Memory, Inc

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HB52RF1289E2-75B

1 GB Registered SDRAM DIMM 128-Mword × 72-bit, 133 MHz Memory Bus, 2-Bank Module (36 pcs of 64 M × 4 Components) PC133 SDRAM

Elpida Memory, Inc 

HB52RF1289E2-75B

AC Characteristics (Ta = 0 to 55°C, VCC = 3.3 V ± 0.3 V, VSS = 0 V) (cont)

HB52RF1289E2-75B

PC133

PC100

CE latency = 4 CE latency = 3

Parameter

PC100

Symbol Symbol Min

Max Min

Max Unit Notes

Command setup time

t CS

Command hold time

t CH

Ref/Active to Ref/Active command tRC

period

Tsi

1.9

—

Thi

1.5

—

Trc

67.5 —

2.6

—

1.6

—

70

—

ns 1

ns 1, 5

ns 1

Active to precharge command period tRAS

Active command to column

t RCD

command (same bank)

Tras 45

Trcd 20

120000 50

—

20

120000 ns 1

—

ns 1

Precharge to active command period tRP

Trp

20

—

20

—

ns 1

Write recovery or data-in to

precharge lead time

t DPL

Tdpl 7.5

—

10

—

ns 1

Active (a) to Active (b) command

t RRD

Trrd 15

—

20

—

ns 1

period

Transition time (rise to fall)

tT

1

5

1

5

ns

Refresh period

t REF

—

64

—

64

ms

Notes: 1. AC measurement assumes tT = 1 ns. Reference level for timing of input signals is 1.5 V.

2. Access time is measured at 1.5 V. Load condition is CL = 50 pF.

3. tLZ (min) defines the time at which the outputs achieves the low impedance state.

4. tHZ (max) defines the time at which the outputs achieves the high impedance state.

5. tCES defines CKE setup time to CK rising edge except power down exit command.

Test Conditions

• Input and output timing reference levels: 1.5 V

• Input waveform and output load: See following figures

• Ambient illuminance: Under 100 lx

input

2.4 V

2.0 V

0.4 V 0.8 V

tT

tT

DQ

CL

Data Sheet E0018H10

12

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