MT9122AE 데이터 시트보기 (PDF) - Mitel Networks
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MT9122AE Datasheet PDF : 32 Pages
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MT9122
Preliminary Information
valid ST-BUS frame pulse is applied to the F0i pin,
the MT9122 will assume ST-BUS operation. If F0i is
tied continuously to Vss the MT9122 will assume SSI
operation.
and ENB2) are used for parsing input/output data
and they must pulse within 125 microseconds of the
rising edge of ENA1. If they are unused, they must
be tied to Vss.
ST-BUS Operation
The ST-BUS PCM interface conforms to Mitel’s ST-
BUS standard and it is used to transport 8 bit
companded PCM data (using one timeslot) or 16 bit
2’s complement linear PCM data (using two
timeslots). Pins ENA1 and ENB1 select timeslots on
PORT1 while pins ENA2 and ENB2 select timeslots
on PORT2. See Table 4 and Figures 5 to 8.
PORT1
Rin/Sout
Enable Pins
ST-BUS Mode
Selection
PORT2
Sin/Rout
Enable Pins
ENB1 ENA1
ENB2 ENA2
0
0 Mode 1. 8 bit companded PCM I/O on 0
0
timeslots 0 & 1.
0
1 Mode 2. 8 bit companded PCM I/O on 0
1
timeslots 2 & 3.
1
0 Mode 3. 8 bit companded PCM I/O on 1
0
timeslots 2 & 3. Includes D & C chan-
nel bypass in timeslots 0 & 1.
1
1 Mode 4. 16 bit 2’s complement linear 1
1
PCM I/O on timeslots 0 - 3.
Table 4 - ST-BUS Mode Select
Note that if the device is in back-to-back or extended
delay configurations, the second timeslot in any ST-
BUS Mode contains undefined data. This means that
the following timeslots contain undefined data:
timeslot 1 in ST-BUS Mode 1; timeslot 3 in ST-BUS
Modes 2 & 3 and timeslots 2 and 3 in ST-BUS Mode
4.
SSI Operation
The SSI PCM interface consists of data input pins
(Rin, Sin), data output pins (Sout, Rout), a variable
rate bit clock (BCLK), and four enable pins
(ENA1,ENB1, ENA2 and ENB2) to provide strobes
for data transfers. The active high enable may be
either 8 or 16 BCLK cycles in duration. Automatic
detection of the data type (8 bit companded or 16 bit
2’s complement linear) is accomplished internally.
The data type cannot change dynamically from one
frame to the next.
In SSI operation, the frame boundary is determined
by the rising edge of the ENA1 enable strobe (see
Figure 9). The other enable strobes (ENB1, ENA2
In SSI operation, the enable strobes may be a mixed
combination of 8 or 16 BCLK cycles allowing the
flexibility to mix 2’s complement linear data on one
port (e.g., Rin/Sout) with companded data on the
other port (e.g., Sin/Rout).
Enable Strobe Pin
Echo Canceller
Port
ENA1
A
1
ENB1
B
1
ENA2
A
2
ENB2
B
2
Table 5 - SSI Enable Strobe Pins
PCM Law and Format Control (LAW, FORMAT)
The PCM companding/coding law used by the
MT9122 is controlled through the LAW and FORMAT
pins. ITU-T G.711 companding curves for µ-Law and
A-Law are selected by the LAW pin. PCM coding
ITU-T G.711 and Sign-Magnitude are selected by the
FORMAT pin. See Table 6.
PCM Code
Sign-Magnitude
FORMAT=0
µ/A-LAW
LAW = 0 or 1
ITU-T (G.711)
FORMAT=1
µ-LAW
LAW = 0
A-LAW
LAW =1
+ Full Scale
1111 1111
1000 0000 1010 1010
+ Zero
1000 0000
1111 1111 1101 0101
- Zero
0000 0000
0111 1111 0101 0101
- Full Scale
0111 1111
0000 0000 0010 1010
Table 6 - Companded PCM
Linear PCM
The 16-bit 2’s complement PCM linear coding
permits a dynamic range beyond that which is
specified in ITU-T G.711 for companded PCM. The
echo-cancellation algorithm will accept 16 bits 2’s
complement linear code which gives a dynamic
range of +15dBm0. Note however that the tone
detectors must be limited to the maximum dynamic
range specified in G.711 (+3.14 or +3.17 dBm0).
8-26
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