OP179GRT(1999) 데이터 시트보기 (PDF) - Analog Devices

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OP179GRT
(Rev.:1999)

Rail-to-Rail High Output Current Operational Amplifiers

Analog Devices 

OP179/OP279

Typical Performance Graphs

100

60

80

VS = +5V

TA = +25؇C

VS = +5V

50 TA = +25؇C

FREQUENCY = 1kHz

40

60

30

40

20

20

10

0

1

10

100

1k

10k

FREQUENCY – Hz

Figure 19. Voltage Noise Density vs.

Frequency

0

0

1

2

3

4

5

COMMON-MODE VOLTAGE – Volts

Figure 20. Voltage Noise Density vs.

Common-Mode Voltage

120

TA = +25؇C

100

VS ؎2.5V

80

60

40

20

0

100

1k

10k

100k

1M

FREQUENCY – Hz

Figure 21. Common-Mode

Rejection vs. Frequency

THEORY OF OPERATION

The OP179/OP279 is the latest entry in Analog Devices’ ex-

panding family of single-supply devices, designed for the multi-

media and telecom marketplaces. It is a high output current

drive, rail-to-rail input /output operational amplifier, powered

from a single +5 V supply. It is also intended for other low

supply voltage applications where low distortion and high out-

put current drive are needed. To combine the attributes of high

output current and low distortion in rail-to-rail input/output

operation, novel circuit design techniques are used.

For example, Figure 1 illustrates a simplified equivalent circuit

for the OP179/OP279’s input stage. It is comprised of two PNP

differential pairs, Q5-Q6 and Q7-Q8, operating in parallel, with

diode protection networks. Diode networks D5-D6 and D7-D8

serve to clamp the applied differential input voltage to the

OP179/OP279, thereby protecting the input transistors against

avalanche damage. The fundamental differences between these

two PNP gain stages are that the Q7-Q8 pair are normally OFF

and that their inputs are buffered from the operational amplifier

inputs by Q1-D1-D2 and Q9-D3-D4. Operation is best under-

stood as a function of the applied common-mode voltage:

When the inputs of the OP179/OP279 are biased midway be-

tween the supplies, the differential signal path gain is controlled

by the resistively loaded (via R7, R8) Q5-Q6. As the input

common-mode level is reduced toward the negative supply

(VNEG or GND), the input transistor current sources, I1 and I3,

are forced into saturation, thereby forcing the Q1-D1-D2 and

Q9-D3-D4 networks into cutoff; however, Q5-Q6 remain

active, providing input stage gain. On the other hand, when the

common-mode input voltage is increased toward the positive

supply, Q5-Q6 are driven into cutoff, Q3 is driven into satura-

tion, and Q4 becomes active, providing bias to the Q7-Q8 dif-

ferential pair. The point at which the Q7-Q8 differential pair

becomes active is approximately equal to (VPOS – 1 V).

VPOS

R1

6k⍀

Q2

R2

3k⍀

Q3

Q4

R3

R4

2.5k⍀

2.5k⍀

D5

Q1

Q5

IN+

D6

Q6 Q9

IN–

D1

D2

I1 I2

D7

D8

D3

R5 R6

D4

Q7 4k⍀ 4k⍀ Q8

R7

2.2k⍀

– VO +

R8

2.2k⍀

I3

VNEG

Figure 22. OP179/OP279 Equivalent Input Circuit

The key issue here is the behavior of the input bias currents in

this stage. The input bias currents of the OP179/OP279 over

the range of common-mode voltages from (VNEG + 1 V) to

(VPOS – 1 V) are the arithmetic sum of the base currents in Q1-

Q5 and Q9-Q6. Outside of this range, the input bias currents

are dominated by the base current sum of Q5-Q6 for input

signals close to VNEG, and of Q1-Q5 (Q9-Q6) for input signals

close to VPOS. As a result of this design approach, the input bias

currents in the OP179/OP279 not only exhibit different ampli-

tudes, but also exhibit different polarities. This input bias cur-

rent behavior is best illustrated in Figure 3. It is, therefore, of

paramount importance that the effective source impedances

connected to the OP179/OP279’s inputs are balanced for opti-

mum dc and ac performance.

–6–

REV. F

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