CD4001 데이터 시트보기 (PDF) - Intersil

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CD4001

CMOS NOR Gate

Intersil 

Specifications CD4000BMS, CD4001BMS, CD4002BMS, CD4025BMS

Schematic and Logic Diagrams

p

5*

n

(12)

3*

(11)

4*

(13)

14 VDD

p

p

p

p

6(10) p

p

p

n

n

8*

9

nnn

p

n

n

p

n

n

INVERTER AND 1 OF 2

GATES (NUMBERS IN

PARENTHESES ARE

TERMINAL NUMBERS

FOR SECOND GATE)

5(12)

3(11)

4(13)

8

7 VSS

6

(10)

LOGIC DIAGRAM

9

CD4000BMS

*ALL INPUTS ARE

PROTECTED BY CMOS

PROTECTION NETWORK

VDD

p

1*

(8, 6, 13) n

p

2*

n

(9, 5, 12)

14 VDD

p

p

n

VSS

p

3

n

(10, 4, 11)

n

7 VSS

1 OF 4 GATES (NUMBERS IN PARANTHESES

ARE TERMINAL NUMBERS FOR OTHER GATES)

1(8, 6,13)

2(9, 5, 12)

3

(10, 4, 11)

LOGIC DIAGRAM

CD4001BMS

14 VDD

p

p pp

p

n

2*

n

(12)

p

n

3*

(11)

np

n

4*

(10)

np

n

5*

n

(9)

p

1

n (13)

1 OF 2 GATES (NUMBERS IN

PARENTHESES ARE TERMINAL 7 VSS

NUMBERS FOR SECOND GATE)

2(12)

3(11)

4(10)

5(9)

1

(13)

LOGIC DIAGRAM

CD4002BMS

p

3*

n

(1, 11)

4*

(2, 12)

5*

(8, 13)

14 VDD

p

p

p

p

6

n

n (9, 10)

p

n

n

p

n

n

1 OF 3 GATES (NUMBERS IN

7 VSS

PARENTHESES ARE TERMINAL

NUMBERS FOR OTHER GATES)

3(1, 11)

4(2, 12)

5(8, 13)

6

(9, 10)

LOGIC DIAGRAM

CD4025BMS

7-655

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