CD4527 데이터 시트보기 (PDF) - Intersil

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CD4527

CMOS BCD Rate Multiplier

Intersil 

CD4527BMS

Timing Diagram

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CLOCK

Qa

Qb

Qc

Qd

R1

R2

R3

R4

OUTPUT (PIN 6)

A ENABLED

B ENABLED

C ENABLED

D ENABLED

INH. OUT

OUTPUT (PIN 6)

PRESET NO. OF 1

PRESET NO. OF 2

PRESET NO. OF 3

PRESET NO. OF 4

PRESET NO. OF 5

PRESET NO. OF 6

PRESET NO. OF 7

PRESET NO. OF 8

PRESET NO. OF 9

FIGURE 11. (SEE LOGIC DIAGRAM)

Chip Dimensions and Pad Layout

Dimensions in parenthesis are in millimeters and are

derived from the basic inch dimensions as indicated.

Grid graduations are in mils (10-3 inch).

METALLIZATION: Thickness: 11kÅ − 14kÅ, AL.

PASSIVATION: 10.4kÅ - 15.6kÅ, Silane

BOND PADS: 0.004 inches X 0.004 inches MIN

DIE THICKNESS: 0.0198 inches - 0.0218 inches

7-1226

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