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T7504 Datasheet PDF : 18 Pages
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T7504 and T5504 Quad PCM Codecs with Filters
Data Sheet
March 1999
Pin Information (continued)
Table 1. Pin Descriptions
Pin
Symbol
Type*
PLCC MQFP
Name/Function
VFXIN3
VFXIN2
VFXIN1
VFXIN0
GSX3
GSX2
GSX1
GSX0
VFRO3
VFRO2
VFRO1
VFRO0
VDD [1:0]
VDDA [1:0]
14
8
16
22
13
9
17
21
12
10
18
20
7, 24
—
15
8
19
26
14
9
20
25
13
10
21
24
3, 31
4, 30
GNDA4 —
18
GNDA3 15
16
GNDA2 11
11
GNDA1 19
23
GNDA0 23
27
DR
4
44
DX
3
43
MCLK
5
1
GNDD
2
41
FSX3
28
36
FSX2
27
35
FSX1
26
34
FSX0
25
33
ASEL
6
2
FSEP
1
37
I Voice Frequency Transmitter Input. Analog inverting input to the uncommitted
operational amplifier at the transmit filter input. Connect the signal to be digitized
to this pin through a resistor RI (see Figure 2).
O Gain Set for Transmitter. Output of the transmit uncommitted operational
amplifier. The pin is the input to the transmit differential filters. Connect the pin to
its corresponding VFXIN through a resistor RF (see Figure 2).
O Voice Frequency Receiver Output. This pin can drive 2000 Ω (or greater) loads.
— 5 V Digital and Analog Power Supplies. All pins must be connected on the circuit
board. Each pin should be bypassed to ground with at least 0.1 µF of capacitance
as close to the device as possible. For the DIP and PLCC packages, VDD serves
both analog and digital internal circuits.
— Analog Grounds. All ground pins must be connected on the circuit board.
I Receive PCM Data Input. The data on this pin is shifted into the device on the fall-
ing edges of MCLK. Data is only entered for valid time slots as defined by the re-
lationship of the pulses on the FSX inputs and the pulse on the FSEP input.
O Transmit PCM Data Output. This pin remains in the high-impedance state except
during active transmit time slots. An active transmit time slot is defined as one in
which a pulse is present on one of the FSx inputs. Data is shifted out on the rising
edge of MCLK.
I Master Clock Input. The frequency must be 2.048 MHz or 4.096 MHz. This clock
serves as the bit clock for all PCM data transfer. A 40% to 60% duty cycle is re-
quired.
— Digital Ground. Ground connection for the digital circuitry. All ground pins must be
connected on the circuit board.
Id Transmit Frame Sync. This signal is an edge trigger and must be high for a min-
imum of one MCLK cycle. This signal must be derived from MCLK. The division ra-
tio is 1:256 or 1:512 (FSX:MCLK). Each FSX input must have a pulse present at the
start of the desired active output time slot. Pulses on the various FSX inputs must
be separated by one or more integer multiples of time slots. An internal pull-down
device is included on each FSX.
Id A-Law/µ-Law Select. A logic low selects µ-law coding. A logic high selects A-law
coding. A pull-down device is included.
I Frame Sync Separation. The pulse width of this 8 kHz signal defines the timing
offset between the transmit and receive frames. Internally generated receive frame
sync pulses are delayed from the corresponding transmit frame sync pulse rising
edge by one less than the FSEP pulse width in negative MCLK edges. If the pulse
width is one MCLK period or less, the transmit and receive frame syncs are made
coincident. Loss of FSEP causes the device to powerdown. If the master clock fre-
quency is 2.048 MHz or 4.096 MHz, delays of 255 or 511 clock pulses are not al-
lowed, respectively. Timing relationships between FSEP, FSXN, and time slot 0 are
given in Figures 6—9.
* Id Indicates a pull-down device is included on this lead.
4
Lucent Technologies Inc.
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