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74HC75N

Quad bistable transparant latch

Philips Electronics 

Philips Semiconductors

74HC75

Quad bistable transparant latch

nD input

LEnn input

VM

tW

tPHL

tPLH

nQ output

VM

nQ output

tPLH

VM

tTHL

tPHL

tTLH

tTLH

tTHL

001aab857

VM = 0.5 × VI.

Fig 9. Waveforms showing the latch enable input (LEnn) pulse width, the latch enable

input to outputs (nQ, nQ) propagation delays and the output transition times

PULSE

VI

GENERATOR

VCC

VO

D.U.T.

RT

CL

mna101

Test data is given in Table 9.

Definitions for test circuit:

RT = Termination resistance should be equal to output impedance Zo of the pulse generator.

CL = Load capacitance including jig and probe capacitance.

Fig 10. Load circuitry for switching times

Table 9:

Supply

VCC

2.0 V

4.5 V

6.0 V

5.0 V

Test data

Input

VI

VCC

VCC

VCC

VCC

tr, tf

6 ns

6 ns

6 ns

6 ns

Load

CL

50 pF

50 pF

50 pF

15 pF

9397 750 13816

Product data sheet

Rev. 03 — 12 November 2004

© Koninklijke Philips Electronics N.V. 2004. All rights reserved.

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