SY100E101(1998) 데이터 시트보기 (PDF) - Micrel
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SY100E101 Datasheet PDF : 3 Pages
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QUAD 4-INPUT
OR/NOR GATE
SY10E101
SY100E101
FEATURES
s 500ps max. propagation delay
s Extended 100E VEE range of –4.2V to –5.5V
s True and complementary outputs
s Fully compatible with industry standard 10KH,
100K I/O levels
s Internal 75KΩ input pulldown resistors
s Fully compatible with Motorola MC10E/100E101
s Available in 28-pin PLCC package
DESCRIPTION
The SY10/100E101 are quad 4-input OR/NOR gates
designed for use in new, high-performance ECL systems.
The E101 features both true and complementary outputs.
BLOCK DIAGRAM
D0a
D0b
Q0
D0c
Q0
D0d
D1a
D1b
Q1
D1c
Q1
D1d
D2a
D2b
Q2
D2c
Q2
D2d
D3a
D3b
Q3
D3c
Q3
D3d
PIN CONFIGURATION
D2d
D2c
D2b
VEE
D2a
D1d
D1c
25 24 23 22 21 20 19
26
18
27
17
28
PLCC
16
1
TOP VIEW
15
2
J28-1
14
3
13
4
12
5 6 7 8 9 10 11
Q2
Q2
VCC
Q1
Q1
Q0
Q0
PIN NAMES
Pin
Dna, Dnb, Dnc, Dnd
Q0-Q3
Q0-Q3
VCCO
Function
Data Inputs
True Outputs
Inverting Outputs
VCC to Output
Rev.: D Amendment: /2
1
Issue Date: May, 1998
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