MC74HC242N 데이터 시트보기 (PDF) - Motorola => Freescale
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MC74HC242N Datasheet PDF : 5 Pages
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Quad 3-State Bus Transceiver
High–Performance Silicon–Gate CMOS
The MC74HC242 is identical in pinout to the LS242. The device inputs
are compatible with Standard CMOS outputs; with pullup resistors, they
are compatible with LSTTL outputs.
This quad bus transceiver is designed for asynchronous two–way
communications between data buses. The states of the Output Enables
(A–to–B Enable and B–to–A Enable) determine both the direction of data
flow (from A to B or from B to A) and the modes of the Data Ports (input,
output, or high–impedance).
• Output Drive Capability: 15 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS and TTL
• Operating Voltage Range: 2 to 6V
• Low Input Current: 1µA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance With the JEDEC Standard No. 7A Requirements
• Chip Complexity: 130 FETs or 32.5 Equivalent Gates
LOGIC DIAGRAM
A Data
Port
3
A1
4
A2
5
A3
6
A4
11
B1
10
B2
9
B3
B Data
Port
8
B4
MC74HC242
14
1
N SUFFIX
PLASTIC PACKAGE
CASE 646–06
ORDERING INFORMATION
MC74HCXXXN Plastic
FUNCTION TABLE
Control Inputs Data Port Status
A–to–B B–to–A
Enable Enable
A
B
H
H
O
I
L
H
Z
Z
H
L
Z
Z
L
L
I
O
I = Input; O = Output, O = Inverting Output
Z = High Impedance
Output
EnableS
1
A–TO–B ENABLE
13
B–TO–A ENABLE
Pin 14 = VCC
Pin 7 = GND
Pins 2, 12 = No Connection
Pinout: 14–Lead Plastic Package (Top View)
B–to–A
VCC Enable NC B1 B2 B3 B4
14 13 12 11 10 9 8
10/95
© Motorola, Inc. 1995
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A–to–B NC A1 A2 A3 A4 GND
Enable
NC = No Connection
1
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