A8259 데이터 시트보기 (PDF) - Altera Corporation
부품명
상세내역
일치하는 목록
A8259 Datasheet PDF : 24 Pages
| |||
a8259 Programmable Interrupt Controller Data Sheet
Programming
& Initialization
The casin[2..0]and casout[2..0] buses, and nsp and cas_en pins
are used to implement the cascade interface. These pins are used when
more than one a8259 functions are interconnected in a master/slave
configuration, expanding the number of interrupts from 8 up to 64.
The a8259 operation depends on initial programming. Two types of
command words are used for programming the a8259: initialization
command words (ICWs) and operation command words (OCWs). ICWs
are used to load the a8259 internal control registers, while the OCWs
permit the microprocessor to initiate variations in the basic operating
modes defined by the ICW registers. Table 2 summarizes how to access
the ICW and OCW registers for programming and initialization (for more
information on ICW and OCW registers, see “Register Descriptions” on
page 62).
Table 2. ICW & OCW Register Access for Programming & Initialization Note (1)
Register
A0
ICW 1
0
ICW 2
1
ICW 3
1
ICW 4
1
OCW 1
1
OCW 2
0
OCW 3
0
Mnemonics
Description
Access Method
D4
D3
1
Don’t Care
Don’t Care
Don’t Care
Don’t Care
0
0
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
0
1
A write with A0 low and D4 high is
interpreted as the beginning of an
initialization sequence.
This register always follows ICW 1.
Sequential access
which starts with ICW 1
and timed by the pulsing
nwr signal.
The use of this register depends on
the value of SINGLE (see Figure 3
on page 61).
The use of this register depends on
the value of IC4 (see Figure 3 on
page 61).
These registers can be accessed Random access
randomly (see “Operation Command
Word Registers” on page 65 for
more details).
Note:
(1) “Don’t Care” indicates that the bit has no address significance for this register access method. However, the bit will
usually have data significance.
To begin an initialization sequence, the a0 pin must be low, and bit 4 of
the din[7..0] bus must be high during a valid write cycle. Figure 3
shows the a8259 initialization sequence flow diagram.
60
Altera Corporation
Share Link: 