SL74HCT163 데이터 시트보기 (PDF) - System Logic Semiconductor
부품명
상세내역
일치하는 목록
SL74HCT163 Datasheet PDF : 9 Pages
| |||
SL74HCT163
AC ELECTRICAL CHARACTERISTICS(VCC=5.0 V ± 10%, CL=50pF,Input tr=tf=6.0 ns)
Symbol
Parameter
fmax
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tTLH, tTHL
CIN
Maximum Clock Frequency (Figures 1,6)
Maximum Propagation Delay, Clock to Q
(Figures 1,6)
Maximum Propagation Delay, Enable T to Ripple
Carry Out (Figures 2,6)
Maximum Propagation Delay, Clock to Ripple
Carry Out (Figures 1,6)
Maximum Output Transition Time, Any Output,
(Figures 1 and 6)
Maximum Input Capacitance
Guaranteed Limit
25 °C to
-55°C
≤85°C ≤125°C
30
24
20
34
43
51
41
51
62
32
40
48
39
49
59
35
44
53
43
54
65
15
19
22
10
10
10
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
pF
Power Dissipation Capacitance (Per Gate)
CPD Used to determine the no-load dynamic power
consumption: PD=CPDVCC2f+ICCVCC+∆ICCVCC
Typical @25°C,VCC=5.0 V
60
pF
TIMING REQUIREMENTS (VCC=5.0 V ± 10%, CL=50pF,Input tr=tf=6.0 ns)
Symbol
Parameter
tsu
Minimum Setup Time, Preset Data Inputs to Clock
(Figure 4)
tsu
Minimum Setup Time, Load to Clock (Figure 4)
tsu
Minimum Setup Time, Reset to Clock (Figure 3)
tsu
Minimum Setup Time, Enable T or Enable P to Clock
(Figure 5)
th
Minimum Hold Time, Clock to Preset Data Inputs
(Figure 4)
th
Minimum Hold Time, Clock to Load (Figure 4)
th
Minimum Hold Time, Clock to Reset (Figure 3)
th
Minimum Hold Time, Clock to Enable T or Enable P
(Figure 5)
trec
Minimum Recovery Time, Load Inactive to Clock
(Figure 4)
tw
Minimum Pulse Width, Clock (Figure 1)
tw
Minimum Pulse Width, Reset (Figure 4)
tr, tf Maximum Input Rise and Fall Times (Figure 1)
Guaranteed Limit
25 °C to
-55°C
≤85°C ≤125°C Unit
30
38
45
ns
27
34
41
ns
32
40
48
ns
40
50
60
ns
10
13
15
ns
3
3
3
ns
3
3
3
ns
3
3
3
ns
25
31
38
ns
16
20
24
ns
16
20
24
ns
500
500
500
ns
SLS
System Logic
Semiconductor
Share Link: 