HI-DAC85V 데이터 시트보기 (PDF) - Intersil
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HI-DAC85V Datasheet PDF : 7 Pages
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HI-DAC80V, HI-DAC85V
Electrical Specifications TA = 25oC, VS ±12V to ±15V (Note 4), Pin 16 to Pin 24, Unless Otherwise Specified (Continued)
HI-DAC80V-5, HI-DAC85V-5
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Slew Rate
10
15
-
V/µs
INTERNAL REFERENCE
Output Voltage
6.250
+6.3
6.350
V
Output Impedance
-
1.5
-
Ω
External Current
Tempco of Drift
-
-
+2.5
mA
-
5
-
ppm/oC
DIGITAL INPUT (Note 2)
Logic Levels
Logic “1”
TTL Compatible At +1µA
+2
-
+5.5
V
Logic “0”
TTL Compatible At -100µA
0
-
+0.8
V
POWER SUPPLY SENSITIVITY (Notes 2, 4)
+15V Supply
-15V Supply
POWER SUPPLY CHARACTERISTICS (Note 4)
-
0.001
0.002
% FSR / %VS
-
0.001
0.002
% FSR / %VS
Voltage Range
+VS
Full Temperature
+11.4
+15
+16.5
V
-VS
Full Temperature
-11.4
-15
-16.5
V
Current
+IS
Full Temperature, VS = ±15V
-
+12
+15
mA
-IS
Full Temperature, VS = ±15V
-
-15
-20
mA
NOTES:
1. Adjustable to zero using external potentiometers.
2. See Definitions.
3. FSR is “Full Scale Range: and is 20V for ±10V range, 10V for ±5V range, etc.
4. The HI-DAC80V/HI-DAC85V will operate with supply voltages as low as ±11.4V. It is recommended that output voltage range -10V to
+10V not be used if the supply voltages are less than ±12.5V.
5. With Gain and Offset errors adjusted to zero at 25oC.
Definitions of Specifications
Digital Inputs
The Hl-DAC80V accepts digital input codes in complementary
binary, complementary offset binary, and complementary
two’s complement binary.
Settling Time
That interval between application of a digital step input, and
final entry of the analog output within a specified window
about the settled value. Intersil Corporation usually specifies
a unipolar 10V full scale step, to be measured from 50% of
the input digital transition, and a window of ±1/2 LSB about
the final value. The device output is then rated according to
the worst (longest settling) case: low to high, or high to low.
In a 12-bit system ±1/2 LSB = ±0.012% of FSR.
TABLE 1.
ANALOG OUTPUT
DIGITAL
INPUT
COMPLE-
MENTARY
STRAIGHT
BINARY
COMPLE-
MENTARY
OFFSET
BINARY
COMPLE-
MENTARY
TWO’S
COMPLEMENT †
MSB...LSB
000...000 + Full Scale + Full Scale
-LSB
100...000 Mid Scale-1 LSB -1 LSB
+ Full Scale
111...111
Zero
- Full Scale
Zero
011...111 +1/2 Full Scale
Zero
- Full Scale
†Invert MSB with external inverter to obtain CTC Coding
10-1037
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