CXB1573R 데이터 시트보기 (PDF) - Sony Semiconductor
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CXB1573R Datasheet PDF : 21 Pages
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CXB1573R
2. Alarm block
In order to operate the alarm block, give the voltage difference between Pins 17 and 18 to set an alarm level
and connect the peak hold capacitor C3 shown in Fig. 3.
This IC has two setting methods of alarm level; one is to connect Pin 19 to VEE and leave Pins 17 and 18 open
to set an alarm level default value (8mV for input conversion). The other is to connect Pin 19 to VEE and set a
desired alarm level using the external resistors REX1, REX2 and REX3 shown in Fig. 3. Connect REX1 between
Pins 17 and 18 or connect REX3 between Pin 18 and Vcc when less alarm level is desired to be set than its
default value; connect REX2 between Pin 17 and Vcc when more alarm level is desired to be set than its default
value. However, the Pin 17 voltage must be higher than that of Pin 18.
This IC also features two-level setting of identification maximum voltage amplitude. The amplitude is set to
40mVp-p when Pin 3 is left open (High level) and it is set to 20mVp-p when Pin 3 is Low level. Therefore, the
noise margin can be increased by setting Pin 3 to Low level when the small signal is input. The relation of input
voltage and peak hold output voltage is shown in Fig. 5.
In the relation between the alarm setting level and hysteresis width, the hysteresis width is designed to
maintain a constant gain (design target value: 6dB) as shown in Fig. 4.
This IC is designed to externally have the capacitor C3, and the C3 value should be set so as to obtain desired
assert time and deassert time settings for the alarm signal.
The electrical characteristics for the SD response assert and deassert times are guaranteed only when
the waveforms are input as shown in the timing chart of Fig. 6.
REX1: 100Ω (when the alarm level is set to 4mV for input conversion.)
REX2: 8kΩ (when the alarm level is set to 10mV for input conversion.)
REX3: 4kΩ (when the alarm level is set to 4mV for input conversion.)
C3: 470pF
The table below shows the alarm logic.
Optical signal input
state
Signal input
Signal interruption
SD
High level
Low level
SD
Low level
High level
The table below shows the output disable function logic.
Optical signal input
state
ODIS: Open High
ODIS: Low
Q
Fixed Low
Data
Q
Fixed High
Data
Ra1, Ra2A and Ra2B values are
typical values.
VCCA
Ra2A
141
Ra1
986
Ra2B
141
VCS
IC interior
17
IC exterior
18 19
From limiting amplifier
Peak Hold
SD-TTL
SDB-TTL
Peak Hold
SD-ECL
SDB-ECL
VCCA
10p
∆V
VCCA
10p
3
19
17
18
21
22
C3
C3
REX2
REX1
REX3
VEE
VCC
VCC
VCC
VCC
Fig. 3
– 13 –
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