HI5800JCD 데이터 시트보기 (PDF) - Intersil

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HI5800JCD

12-Bit, 3MSPS, Sampling A/D Converter

Intersil 

Functional Block Diagram

HI5800

REFOUT

REFIN

REFERENCE

ADJ+

ADJ-

VIN

S AND H

7-BIT

FLASH

7-BIT

LATCH

7-BIT

LATCH

7-BIT

DAC

X32

CONTROL

LOGIC

AND

TIMING

D0 (LSB)

D1

D2

DIGITAL

OUTPUTS

D10

D11 (MSB)

OVF

IRQ

CS

CONV

OE

AO

AVCC AVEE DVCC DVEE AGND DGND

RGADJ ROADJ

Typical Application Schematic

C23

C22

C1

+10µF

0.1µF

0.01µF

VIN

CONV

OE

A0

CS

HI5800

(22) (LSB) D0

(23) D1

REF_IN (1)

REF_OUT (5)

AGND (7)

AGND (12)

AGND (31)

DGND (19)

DGND (32)

(24) D2

(25) D3

(26) D4

(27) D5

(28) D6

(29) D7

(34) D8

(35) D9

VIN (6)

(36) D10

(37) (MSB) D11

CONV (17)

OE (16)

A0 (14)

CS (15)

(40) IRQ

(39) OVF

(18) DVEE

(33) DVCC

(20)

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

D10

D11

IRQ

OVF

BNC

GND

10µF, 0.1µF, AND 0.01µF CAPS ARE PLACED

AS CLOSE TO PART AS POSSIBLE

0.1µF

+

10µF

0.1µF +10µF

AVCC

R9

10K

R10

10K

AVEE

R11

10K

RO_ADJ (2)

RG_ADJ (3)

(4) AVCC

(11)

(21) AVCC

(38)

ADJ+ (8)

ADJ- (9)

(10) AVEE

(13) (30)

0.1µF +10µF

0.1µF

+

10µF

4-2

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