M64897GP 데이터 시트보기 (PDF) - MITSUBISHI ELECTRIC
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M64897GP Datasheet PDF : 8 Pages
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MITSUBISHI ICs (TV)
M64897GP
PLL FREQUENCY SYNTHESIZER WITH DC-DC CONVERTER FOR PC
DATA CORDING EXAMPLE
Write mode format example
Byte
Address Byte
Devider Byte1
Devider Byte2
Control Byte1
Band SW Byte
MSB
LSB Condition in data setting
1
1
0
0
0
1
1
0
1 ADS input VCC1
0
1
0
0
0
0
0
0
1
Divider ratio N=16544
1
0
1
0
0
0
0
0
1
1
1
0
0
0
0
1
0
1 fREF divider ratio 1/1024
0
0
0
0
1
0
0
0
1 BS4 output ON
fVCO=N×8×fREF
=16544×8×(4MHz/1024)=517MHz
Read mode format example (Loop locked)
Byte
Address Byte
Status Byte
MSB
LSB
Condition in device
ADS Applied voltage
1
1
0
0
0
1
1
1
1
0.9∗VCC1 to VCC1
ADS Applied voltage
0
1
1
1
1
0
1
1
1
0.45∗VCC1 to 0.6∗VCC1
Use data input for "1" so that the data of Read mode and Write
mode return ACK signal "0" to micro computer in 9bits of each byte.
TEST MODE DATA SET UP METHOD
Test Mode Bit Set Up
X
: Random, 0 or 1. normal "0"
MA1 ,MA0 : Programmabule Address Bit
Address input voltage
0 to 0.1∗VCC1
Always valid
0.4∗VCC1 to 0.6∗VCC1
0.9∗VCC1 to VCC1
MA1
0
0
1
1
MA0
0
1
0
1
N14 to N0 : How to set dividing ratio of the programable the divider
Divider ratio=N14(214=16384)+ ⋅ ⋅ ⋅ +N0(20=1)
Therefore, the range of divider N is 1,024 to 32,768
Example) fvco=fREF×8×N
=3.90625×8×N
=31.25×N (kHz)
T2, T1, T0 : Setting up for the test mode
T2 T1 T0 Charge pump
0 0 X Normal operation
0 1 X High impedance
1 1 0 Sink
1 1 1 Source
1 0 0 High impedance
1 0 1 High impedance
12 pin condition
Mode
ADC input Normal operation
ADC input Test mode
ADC input Test mode
ADC input Test mode
fREF output Test mode
f1/N output Test mode
RSa, RSb : Set up for the reference Frequency divider ratio
RSa
RSb
1
1
0
1
X
0
Divider ratio
1/512
1/1024
1/640
OS : Set up the tuning amplifier
OS
Tuning voltage output
0
ON
1
OFF
Mode
Normal
Test
POR : Power on reset flag. "1" output at reset
FL : Lock detector flag. "1" output at locked, "0" output at unlocked
6
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