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전자부품 반도체 검색엔진( 무료 PDF 다운로드 ) - 데이터시트뱅크

AT43101 데이터 시트보기 (PDF) - Atmel Corporation

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AT43101 Datasheet PDF : 14 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
AC Read Characteristics
Symbol
Parameter
tia(A)
Delay to IA[24:0], from A[24:0]
tda(A)
Data access time, from A[8:0] to D[7:0]
ten(CE)
Output enable time from CE*
ten(OE)
Output enable time from OE*
ten(REG)
Output enable time from REG*
tdis(CE)
tdis(OE)
Output disable time from CE*
Output disable time from OE*
tdis(REG)
Output disable time from REG*
tioel(A0)
Delay to IOEL*, IOEH* assertion from A0
tioel(CE)
Delay to IOEL*, IOEH* assertion from CE*
tioel(OE)
Delay to IOEL*, IOEH* assertion from OE*
tioel(REG)
Delay to IOEL*, IOEH* assertion from REG*
tioeh(A0)
Delay to IOEL*, IOEH* de-assertion from A0
tioeh(CE)
Delay to IOEL*, IOEH* de-assertion from CE*
tioeh(OE)
Delay to IOEL*, IOEH* de-assertion from OE*
tioeh(REG)
Delay to IOEL*, IOEH* de-assertion from REG*
tv(A)
Delay to data change, from change of address
td(ID)
Delay from ID[15:0] to D[15:0]
tice(A)
Delay to ICE[7:0]* from DEC[2:0], SEL[1:0], SGL/DBL*
tice(REG)
Delay to ICE[7:0]* from REG*
tice(CE)
Delay to ICE[7:0]* from CE1*, CE2*
Ten (reset)
Chip active enable time from reset
Tdis (reset)
Chip active disable time from reset
Notes:
1. Either or both of CE1*, CE2* assert according to function truth table.
2. REG* asserted only for Attribute Memory read.
3. tda(A) applies to Attribute Memory read. Access time for Common Memory
read is derived from tia(A), td(ID), and external device access time.
4. Symmetrical for assertion and de-assertion. Also applies to write cycles.
5. Not shown in timing diagram.
Input Test Waveforms and Measurement Level
VDD
VDD/2
0V
AC MEASUREMENT LEVEL
tR1tƒ<5 ns, test load capacitance is 50pf
10
AT43101
Min
Max Notes
0 ns
30 ns
250 ns
3
5 ns
36 ns
1
5 ns
36 ns
36 ns
2
58 ns
1
58 ns
58 ns
28 ns
28 ns
1
25 ns
28 ns
2
28 ns
28 ns
1
25 ns
28 ns
2
0 ns
27 ns
38 ns
4
38 ns
4
30 ns
4
50 ns
5
50 ns
5

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