MBM29PL3200BE 데이터 시트보기 (PDF) - Fujitsu
부품명
상세내역
일치하는 목록
MBM29PL3200BE Datasheet PDF : 59 Pages
| |||
MBM29PL3200TE/BE70/90
(Continued)
The device provides truly high performance non-volatile Flash memory solution. The device offers fast page
access times of 25 ns and 35 ns with random access times of 70 ns and 90 ns, allowing operation of high-speed
microprocessors without wait states. To eliminate bus contention, the device has separate chip enable (CE),
write enable (WE) and output enable (OE) controls. The page size is 8 words or 4 double words.
The device is command set compatible with JEDEC standard E2PROMs. Commands are written to the command
register using standard microprocessor write timings. Register contents serve as input to an internal state-
machine which controls the erase and programming circuitry. Write cycles also internally latch addresses and
data needed for the programming and erase operations. Reading data out of the device is similar to reading
from 5.0 V and 12.0 V Flash or EPROM devices.
The device is programmed by executing the program command sequence. This will invoke the Embedded
ProgramTM * Algorithm, which is an internal algorithm that automatically times the program pulse widths and
verifies proper cell margins. Typically, each sector can be programmed and verified in about 2.2 seconds. Erase
is accomplished by executing the erase command sequence. This will invoke the Embedded EraseTM * Algorithm,
which is an internal algorithm that automatically preprograms the array if it is not already programmed before
executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies
proper cell margins.
Any individual sector is typically erased and verified in 4.8 second. (If already preprogrammed.)
The device also features a sector erase architecture. The sector mode allows each sector to be erased and
reprogrammed without affecting other sectors. The device is erased when shipped from the factory.
The device features single 3.0 V power supply operation for both read and write functions. Internally generated
and regulated voltages are provided for the program and erase operations. A low VCC detector automatically
inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ7,
by the Toggle Bit feature on DQ6, output pin. Once the end of a program or erase cycle has been completed,
the device internally resets to the read mode.
Fujitsu’s Flash technology combines years of Flash memory manufacturing experience to produce the highest
levels of quality, reliability, and cost effectiveness. The device memory electrically erases all bits within a sector
simultaneously via Fowler-Nordhiem tunneling. The words/double words are programmed one word/double word
at a time using the EPROM programming mechanism of hot electron injection.
*: Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc.
s FEATURES
• 0.23 µm Process Technology
• Single 3.0 V read, program and erase
Minimized system level power requirements
• High Performance Page Mode
25 ns maximum page access time (70 ns random access time)
• 8 words Page ( × 16) /4 double words ( × 32) size
• Compatible with JEDEC-standard commands
Uses same software commands as E2PROMs
• Compatible with JEDEC-standard world-wide pinouts
90-pin SSOP (Package suffix : PFV)
84-ball FBGA (Package suffix : PBT)
• Minimum 100,000 program/erase cycles
• Sector erase architecture
One 16 K word, two 8 K words, one 96 K word, and fifteen 128 K words sectors in word mode ( × 16)
One 8 K double word, two 4 K double words, one 48 K double word, and fifteen 64 K double words sectors in
double word mode ( × 32)
Any combination of sectors can be concurrently erased. Also supports full chip erase
2
Share Link: 