SN74LS373 데이터 시트보기 (PDF) - ON Semiconductor
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SN74LS373
ON Semiconductor
SN74LS373 Datasheet PDF : 8 Pages
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SN74LS373, SN74LS374
CONNECTION DIAGRAM DIP (TOP VIEW)
SN74LS373
VCC O7 D7 D6 O6 O5 D5 D4 O4 LE
20 19 18 17 16 15 14 13 12 11
SN74LS374
VCC O7 D7 D6 O6 O5 D5 D4 O4 CP
20 19 18 17 16 15 14 13 12 11
1 2 3 4 5 6 7 8 9 10
OE
O0
D0
D1
O1
O2
D2
D3
O3 GND
NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual InĆLine Package.
1 2 3 4 5 6 7 8 9 10
OE O0 D0 D1 O1 O2 D2 D3 O3 GND
PIN NAMES
D0 - D7
LE
CP
OE
O0 - O7
Data Inputs
Latch Enable (Active HIGH) Input
Clock (Active HIGH Going Edge) Input
Output Enable (Active LOW) Input
Outputs
NOTES:
ąa) 1 TTL Unit Load (U.L.) = 40 mA HIGH/1.6 mA LOW.
LOADING (Note a)
HIGH
LOW
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
65 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
15 U.L.
LS373
TRUTH TABLE
Dn
LE
OE On
Dn
H
H
L
H
H
L
H
L
L
L
X
L
L
Q0
X
X
X
H
Z*
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
* Note: Contents of flip-flops unaffected by the state of the Output Enable input (OE).
LS374
LE
OE On
L
H
L
L
X
H
Z*
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