M74HCT563RM13TR 데이터 시트보기 (PDF) - STMicroelectronics

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M74HCT563RM13TR

OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT INVERTING

STMicroelectronics 

M74HCT563

OCTAL D-TYPE LATCH

WITH 3 STATE OUTPUT INVERTING

s HIGH SPEED:

tPD = 21ns (TYP.) at VCC = 4.5V

s LOW POWER DISSIPATION:

ICC = 4µA(MAX.) at TA=25°C

s COMPATIBLE WITH TTL OUTPUTS :

VIH = 2V (MIN.) VIL = 0.8V (MAX)

s BALANCED PROPAGATION DELAYS:

tPLH ≅ tPHL

s SYMMETRICAL OUTPUT IMPEDANCE:

|IOH| = IOL = 6mA (MIN)

s PIN AND FUNCTION COMPATIBLE WITH

74 SERIES 563

DESCRIPTION

The M74HCT563 is an high speed CMOS OCTAL

LATCH WITH 3-STATE OUTPUTS fabricated

with silicon gate C2MOS technology.

This 8-BIT D-Type latches is controlled by a latch

enable input (LE) and output enable input (OE).

While the LE input is held at a high level, the Q

outputs will follow the data input inversely. When

the LE is taken low, the Q outputs will be latched

inversely at the logic level of D input data.

While the OE input is at low level, the eight outputs

will be in a normal logic state (high or low logic

level) and while OE is at high level the outputs will

be in a high impedance state.

DIP

SOP

TSSOP

ORDER CODES

PACKAGE

TUBE

T&R

DIP

SOP

TSSOP

M74HCT563B1R

M74HCT563M1R M74HCT563RM13TR

M74HCT563TTR

The 3-State output configuration and the wide

choice of outline make bus organized system

simple.

The M74HCT563 is designed to directly interface

HSC2MOS systems with TTL and NMOS

components.

All inputs are equipped with protection circuits

against static discharge and transient excess

voltage.

PIN CONNECTION AND IEC LOGIC SYMBOLS

August 2001

1/11

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