IN74ALS373DW 데이터 시트보기 (PDF) - Integral Corp.
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IN74ALS373DW Datasheet PDF : 4 Pages
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TECHNICAL DATA
IN74ALS373
Octal D-Type 3-State Transparent Latch
These 8-bit registers feature totem-pole 3-State outputs designed
specifically for driving highly-capacitive or relatively low-impedance
loads. The high-impedance state and increased high-logic-level drive
provide these registers with the capability of being connected directly
to and driving the bus lines in a bus-organized system without need for
interface or pull-up components. They are particularly attractive for
implementing buffer registers, I/O ports, bidirectional bus drivers, and
working registers.
The eight latches of the ALS373 are transparent D-type latches.
While the Latch Enable is high the Q outputs will follow the data(D)
inputs. When the enable is taken low the output will be latched at the
level of the data that was set up.
A buffered output control input can be used to place the eight
outputs in either a normal logic state (high or low logic levels) or a
high-impedance state. In the high-impedance state the outputs neither
load nor drive the bus lines significanty.
The output control does not affect the internal operation of the
latches. That is, the old data can be retained or new data can be entered
even while the outputs are off.
• Switching specifications at 50 pF
• Switching specifications guaranteed over full temperature and
VCC range
• Functionally and pin for pin compatible with LS TTL counterpart
• Improved AC performance over LS373 at approximately half the
power
• TRI-STATE buffer-type outputs drive bus lines directly
ORDERING INFORMATION
IN74ALS373N Plastic
IN74ALS373DW SOIC
TA = -10° to 70° C
for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
PIN 20=VCC
PIN 10 = GND
FUNCTION TABLE
Inputs
Output Latch D
Enable Enable
L
H
H
L
H
L
L
L
X
H
X
X
X = Don’t Care
Z = High Impedance
Output
Q
H
L
No Change
Z
1
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