SL74LV374N 데이터 시트보기 (PDF) - System Logic Semiconductor

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SL74LV374N

OCTAL D-TIME FLIP-FLOP; POSITIVE EDGE-TRIGGER (3-StatE)

System Logic Semiconductor 

SL74LV374

AC CHARACTERISTICS (CL=50 pF, tLH = tHL = 6.0 ns)

Symbol

Parameter

Test

VCC,

conditions V

25° C

Limits

-40°C to

85° C

125° C

min max min max min max

tPHL, tPLH

Propagation

from CP to Qn delay

Figure 1

1.2 - 180 - 230 - 270

2.0 - 45 - 56 - 68

3.0 - 27 - 34 - 41

tPHZ tPLZ

Propagation

from OE to Qn delay

Figure 3

1.2 - 160 - 200 - 240

2.0 - 38 - 57 - 68

3.0 - 25 - 36 - 43

tPZH tPZL Propagation

from OE to Qn delay

Figure 3

1.2 - 160 - 200 - 240

2.0 - 38 - 48 - 58

3.0 - 23 - 29 - 35

tTHL, tTLH

HIGH-to-LOW

and LOW-to-

HIGH transition

time

Figure 1

1.2 - 75 - 100 - 120

2.0 - 16 - 20 - 24

3.0 - 10 - 13 - 15

tW

Clock pulse

Figure 1

width HIGH or

LOW

1.2 250 - 350 - 540 -

2.0 18 - 23 - 28 -

3.0 11 - 14 - 17 -

tSU

Set-up time Dn Figure 2

to CP

1.2 45 - 50 - 100 -

2.0 13 - 17 - 20 -

3.0 8 - 10 - 12 -

tH

Hold time Dn to Figure 2

CP

1.2 25 - 25 - 25 -

2.0 5 - 5 - 5 -

3.0 5 - 5 - 5 -

fc

CP naximum Figure 1

pulse frequency

2.0 - 27 - 22 - 18

3.0 - 46 - 37 - 31

CI

Input

capacitance

3.0 - 7 - - - -

CPD

Power

VI = 0 V or VCC 3.0 - 34 -

-

-

-

dissipation

capacitance (per

flip-flop)

Unit

ns

MHz

pF

SLS System Logic

Semiconductor

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