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MC74HC245AFER Datasheet PDF : 8 Pages
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MC74HC245A
Octal 3-State Noninverting
Bus Transceiver
High–Performance Silicon–Gate CMOS
The MC74HC245A is identical in pinout to the LS245. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
The HC245A is a 3–state noninverting transceiver that is used for
2–way asynchronous communication between data buses. The device
has an active–low Output Enable pin, which is used to place the I/O
ports into high–impedance states. The Direction control determines
whether data flows from A to B or from B to A.
• Output Drive Capability: 15 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 to 6 V
• Low Input Current: 1 µA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 308 FETs or 77 Equivalent Gates
A
DATA
PORT
A1 2
A2 3
A3 4
A4 5
A5 6
A6 7
A7 8
A8 9
LOGIC DIAGRAM
18 B1
17 B2
16 B3
15 B4
14 B5
13 B6
12 B7
11 B8
B
DATA
PORT
DIRECTION 1
OUTPUT ENABLE 19
PIN 10 = GND
PIN 20 = VCC
FUNCTION TABLE
Control Inputs
Output
Enable
Direction
Operation
L
L
Data Transmitted from Bus B to Bus A
L
H
Data Transmitted from Bus A to Bus B
H
X
X = don’t care
Buses Isolated (High–Impedance State)
http://onsemi.com
20
1
20
1
PDIP–20
N SUFFIX
CASE 738
SOIC WIDE–20
DW SUFFIX
CASE 751D
MARKING
DIAGRAMS
20
MC74HC245AN
AWLYYWW
1
20
HC245A
AWLYYWW
1
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
PIN ASSIGNMENT
DIRECTION 1
A1 2
A2 3
A3 4
A4 5
A5 6
A6 7
A7 8
A8 9
GND 10
20 VCC
19 OUTPUT ENABLE
18 B1
17 B2
16 B3
15 B4
14 B5
13 B6
12 B7
11 B8
ORDERING INFORMATION
Device
Package Shipping
MC74HC245AN
PDIP–20 1440 / Box
MC74HC245ADW
SOIC–WIDE 38 / Rail
MC74HC245ADWR2 SOIC–WIDE 1000 / Reel
© Semiconductor Components Industries, LLC, 2000
1
March, 2000 – Rev. 8
Publication Order Number:
MC74HC245A/D
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