SL74HC533N 데이터 시트보기 (PDF) - System Logic Semiconductor
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SL74HC533N Datasheet PDF : 6 Pages
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SL74HC533
AC ELECTRICAL CHARACTERISTICS(CL=50pF,Input tr=tf=6.0 ns)
Symbol
Parameter
VCC
Guaranteed Limit
V 25 °C to ≤85°C ≤125°C Unit
-55°C
tPLH, tPHL Maximum Propagation Delay, Input D to Q
(Figures 1 and 5)
2.0 175
220
265
ns
4.5 35
44
53
6.0 30
37
45
tPLH, tPHL Maximum Propagation Delay, Latch Enable to Q
2.0 175
220
265
ns
(Figures 2 and 5)
4.5 35
44
53
6.0 30
37
45
tPLZ, tPHZ Maximum Propagation Delay , Output Enable to Q 2.0 150
190
225
ns
(Figures 3 and 6)
4.5 30
38
45
6.0 26
33
38
tPZL, tPZH Maximum Propagation Delay , Output Enable to Q 2.0 150
190
225
ns
(Figures 3 and 6)
4.5 30
38
45
6.0 26
33
38
tTLH, tTHL Maximum Output Transition Time, Any Output
2.0 60
75
90
ns
(Figures 1 and 5)
4.5 12
15
18
6.0 10
13
15
CIN
Maximum Input Capacitance
COUT Maximum Three-State Output Capacitance
(Output in High-Impedance State)
-
10
10
10
pF
-
15
15
15
pF
Power Dissipation Capacitance (Per Latch)
CPD Used to determine the no-load dynamic power
consumption:
PD=CPDVCC2f+ICCVCC
Typical @25°C,VCC=5.0 V
37
pF
TIMING REQUIREMENTS(CL=50pF,Input tr=tf=6.0 ns)
Symbol
Parameter
VCC
Guaranteed Limit
V 25 °C to -55°C ≤85°C ≤125°C Unit
tsu
Minimum Setup Time, Input D to
2.0
75
Latch Enable (Figure 4)
4.5
15
6.0
13
95
110
ns
19
22
16
19
th
Minimum Hold Time, Latch Enable to 2.0
5
Input D(Figure 4)
4.5
5
6.0
5
5
5
ns
5
5
5
5
tw
Minimum Pulse Width, Latch Enable
2.0
80
(Figure 2)
4.5
16
6.0
14
100
120
ns
20
24
17
20
tr, tf Maximum Input Rise and Fall Times
2.0
1000
(Figure 1)
4.5
500
6.0
400
1000
1000
ns
500
500
400
400
SLS
System Logic
Semiconductor
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