MC54HC240A 데이터 시트보기 (PDF) - Motorola => Freescale

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MC54HC240A

Octal 3-State Inverting Buffer/Line Driver/Line Receiver

Motorola => Freescale 

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Octal 3-State Inverting Buffer/

Line Driver/Line Receiver

High–Performance Silicon–Gate CMOS

The MC54/74HC240A is identical in pinout to the LS240. The device

inputs are compatible with standard CMOS outputs; with pullup resistors,

they are compatible with LSTTL outputs.

This octal noninverting buffer/line driver/line receiver is designed to be

used with 3–state memory address drivers, clock drivers, and other

sub–oriented systems. The device has inverting outputs and two active–low

output enables.

The HC240A is similar in function to the HC241A and HC244A.

• Output Drive Capability: 15 LSTTL Loads

• Outputs Directly Interface to CMOS, NMOS, and TTL

• Operating Voltage Range: 2 to 6 V

• Low Input Current: 1 µA

• High Noise Immunity Characteristic of CMOS Devices

• In Compliance with the Requirements Defined by JEDEC Standard

No. 7A

• Chip Complexity: 120 FETs or 30 Equivalent Gates

A1 2

A2 4

A3 6

DATA

INPUTS

A4 8

B1 11

B2 13

B3 15

B4 17

LOGIC DIAGRAM

18 YA1

16 YA2

14 YA3

12 YA4

9 YB1

INVERTING

OUTPUTS

7 YB2

5 YB3

3 YB4

OUTPUT ENABLE A 1

ENABLES ENABLE B 19

PIN 20 = VCC

PIN 10 = GND

MC54/74HC240A

20

1

J SUFFIX

CERAMIC PACKAGE

CASE 732–03

20

1

20

1

N SUFFIX

PLASTIC PACKAGE

CASE 738–03

DW SUFFIX

SOIC PACKAGE

CASE 751D–04

20

1

DT SUFFIX

TSSOP PACKAGE

CASE 948E–02

ORDERING INFORMATION

MC54HCXXXAJ

MC74HCXXXAN

MC74HCXXXADW

MC74HCXXXADT

Ceramic

Plastic

SOIC

TSSOP

PIN ASSIGNMENT

ENABLE A 1

A1 2

YB4 3

A2 4

YB3 5

A3 6

YB2 7

A4 8

YB1 9

GND 10

20 VCC

19 ENABLE B

18 YA1

17 B4

16 YA2

15 B3

14 YA3

13 B2

12 YA4

11 B1

FUNCTION TABLE

Inputs

Enable A,

Enable B A, B

Outputs

YA, YB

L

L

H

L

H

L

H

X

Z

Z = high impedance

10/95

© Motorola, Inc. 1995

1

REV 6

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