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AD7841

Octal 14-Bit, Parallel Input, Voltage-Output DAC

Analog Devices 

AD7841

ABSOLUTE MAXIMUM RATINGS1, 2

(TA = 25°C unless otherwise noted)

VCC to GND3 . . . . . . . . . . . . . . –0.3 V, +7 V or VDD + 0.3 V

(Whichever Is Lower)

VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +17 V

VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V, –17 V

Digital Inputs to GND . . . . . . . . . . . . . . –0.3 V, VCC + 0.3 V

VREF(+) to VREF(–) . . . . . . . . . . . . . . . . . . . . . –0.3 V, +18 V

VREF(+) to GND . . . . . . . . . . . . . . . VSS – 0.3 V, VDD + 0.3 V

VREF(–) to GND . . . . . . . . . . . . . . . VSS – 0.3 V, VDD + 0.3 V

DUTGND to GND . . . . . . . . . . . . . VSS – 0.3 V, VDD + 0.3 V

VOUT (A–H) to GND . . . . . . . . . . . . VSS – 0.3 V, VDD + 0.3 V

Operating Temperature Range

Industrial (A Version) . . . . . . . . . . . . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150°C

MQFP Package

Power Dissipation . . . . . . . . . . . . . . . . . (TJ Max – TA)/θJA

θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 95°C/W

Lead Temperature ............................JEDEC Industry Standard

Soldering ......................................................................J-STD-020

ESD .................................................................................. >4000 V

NOTES

1Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the

device at these or any other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect device reliability.

2Transient currents of up to 100 mA will not cause SCR latch-up.

3VCC must not exceed VDD by more than 0.3 V. If it is possible for this to happen

during power supply sequencing, the following diode protection scheme will ensure

protection.

VDD

VCC

IN4148

HP5082-2811

VDD

VCC

AD7841

PIN CONFIGURATION

44 43 42 41 40 39 38 37 36 35 34

DUTGND_AB 1

VOUTA 2

VREF(–)AB 3

VREF(+)AB 4

VDD 5

VSS 6

LDAC 7

A2 8

A1 9

A0 10

CS 11

PIN 1

IDENTIFIER

AD7841

TOP VIEW

(Not to Scale)

33 DUTGND_GH

32 VOUTH

31 VREF(–)GH

30 VREF(+)GH

29 CLR

28 DB13

27 DB12

26 DB11

25 DB10

24 DB9

23 DB8

12 13 14 15 16 17 18 19 20 21 22

–4–

REV. B

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