MT89L80AN 데이터 시트보기 (PDF) - Mitel Networks

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MT89L80AN

CMOS ST-BUS™ FAMILY Digital Switch

Mitel Networks 

MT89L80

Advance Information

AC Electrical Characteristics† - Clock Timing (Figures 9 and 10)

Characteristics

Sym Min Typ‡ Max Units

Test Conditions

1

Clock Period*

tCLK 220 244 300

ns

2 I Clock Width High

3 N Clock Width Low

4

P

U

Clock Transition Time

5 T Frame Pulse SetupTime

6 S Frame Pulse Hold Time

tCH

85 122 150 ns

tCL

85 122 150 ns

tCTT

10

ns

tFPS

10

190 ns

tFPH

10

190 ns

7

Frame Pulse Width

tFPW

244

ns

† Timing is over recommended temperature & power supply voltages.

‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.

* Contents of Connection Memory are not lost if the clock stops, however, ST-BUS outputs go into the high impedance state.

NB: Frame Pulse is repeated every 512 cycles of C4i.

C4i

F0i

BIT

CELLS

Channel 31

Bit o

Channel 0

Bit 7

Figure 9- Frame Alignment

VHM

C4i

VLM

F0i VHM

VLM

2-12

tCLK

tCL

tCTT

tFPH

tCHL

tFPS

tCTT

tFPH

tFPW

Figure 10 - Clock Timing

tCH

tFPS

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