CXD2464R 데이터 시트보기 (PDF) - Sony Semiconductor
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CXD2464R Datasheet PDF : 97 Pages
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CXD2464R
2. AC characteristics
(VDD = 5.0 ± 0.5V, VSS = 0V, Topr = –20 to +75°C)
Item
Symbol Applicable pins
Min.
Typ.
Max. Conditions Unit
XGA, Mac16 16.0
Clock input cycle
CKI1, 2 SVGA
20.0
Output rise time
Output fall time
VGA
30.0
tr
All outputs
tf
All outputs
20 CL = 30pF
ns
20 CL = 30pF
Cross-point time difference ∆t
HCK1, 2
–10
Output rise delay time
tpr
All outputs
Output fall delay time
tpf
All outputs
HCK1 Duty
tH/(tH + tL) HCK1
48
HCK2 Duty
tL/(tH + tL) HCK2
48
10 CL = 30pF
15 CL = 30pF
15 CL = 30pF
52 CL = 30pF
%
52 CL = 30pF
Note) The minimum value for the clock input cycle (CKI1) when using the built-in double-speed controller is
30.0ns.
3. Serial transfer AC characteristics
(VDD = 5.0 ± 0.5V, Vss = 0V, Topr =–20 to +75°C)
Symbol
ts0
ts1
th0
th1
tw1L
tw1H
tw2
tw3
Item
SCTR setup time with respect to rise of SCLK
SDAT setup time with respect to rise of SCLK
SCTR hold time with respect to rise of SCLK
SDAT hold time with respect to rise of SCLK
SCLK L level pulse width
SCLK H level pulse width
Min.
Typ.
Max.
4Tns
2Tns
4Tns
2Tns
2Tns
2Tns
5Tns
5Tns
T: Master clock cycle (ns)
Note) Consider the frequency at free run (no signal). When the above characteristic specification is not
satisfied at free run, operating guarantee is not performed as serial transfer.
4. External clock input AC characteristics
(VDD = 5.0 ± 0.5V, Vss = 0V, Topr = –20 to +75°C)
Symbol
ts0
th0
twL
twH
Item
HSYNC setup time with respect to rise of CKI1/2
HSYNC hold time with respect to rise of CKI1/2
CKI1/2 L level pulse width
CKI1/2 H level pulse width
Min.
Typ.
Max.
2ns
6ns
6ns T/2ns
6ns T/2ns
T: Master clock cycle (ns)
Note) During external clock input, set serial data HR to L. The pulse synchronized with the horizontal sync
signal is generated by detecting the front edge of horizontal sync signal and then resetting internal PLL
counter.
–6–
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