TC58256AFTI 데이터 시트보기 (PDF) - Toshiba

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TC58256AFTI

256-MBIT (32M X 8 BITS) CMOS NAND E2PROM

Toshiba 

Read Cycle (1) Timing Diagram

TC58256AFTI

CLE

tCLS tCLH

tCS

tCH

CE

tWC

tCEH

tCRY

WE

tALH tALS

tALH

tAR2

ALE

RE

tDS tDH

tR

tDS tDH

tDS tDH

tWB

tDS tDH

I/O1

to I/O8

RY/BY

00H

A0 toA7 A9 toA16 A17toA24

Column address

N*

* Read Operation using 00H Command N: 0 to 255

tRR

tRC

tREA

DOUT DOUT DOUT

N N+1 N+2

DOUT

527

tRB

: VIH or VIL

Read Cycle (1) Timing Diagram: When Interrupted by CE

CLE

tCLS tCLH

tCS

tCH

CE

tWC

tCHZ

WE

tALH tALS

tALH

tAR2

ALE

RE

tDS tDH

tR

tDS tDH

tDS tDH

tWB

tDS tDH

I/O1

to I/O8

RY/BY

00H

A0 toA7 A9 t oA16 A17toA24

Column address

N*

* Read Operation using 00H Command N: 0 to 255

tRR

tRC

tREA

tOH

tRHZ

DOUT DOUT DOUT

N

N+1 N+2

: VIH or VIL

2001-05-30 9/33

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