M74HC573M1R(1993) 데이터 시트보기 (PDF) - STMicroelectronics
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M74HC573M1R
(Rev.:1993)
(Rev.:1993)
STMicroelectronics
M74HC573M1R Datasheet PDF : 13 Pages
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M54/74HC563
M54/74HC573
OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT
HC563 INVERTING - HC573 NON INVERTING
. HIGH SPEED
tPD = 13 ns (TYP.) AT VCC = 5 V
. LOW POWER DISSIPATION
ICC = 4 µA (MAX.) AT TA = 25 °C
. HIGH NOISE IMMUNITY
VNIH = VNIL = 28 % VCC (MIN.)
. OUTPUT DRIVE CAPABILITY
15 LSTTL LOADS
. SYMMETRICAL OUTPUT IMPEDANCE
IOL = IOH= 6 mA (MIN.)
. BALANCED PROPAGATION DELAYS
tPLH = tPHL
. WIDE OPERATING VOLTAGE RANGE
VCC (OPR) = 2 V TO 6 V
. PIN AND FUNCTION COMPATIBLE
WITH 54/74LS563/573
DESCRIPTION
B1R
(Plastic Package)
F1R
(Ceramic Package)
M 1R
(Micro Package)
C1R
(Chip Carrier)
ORDER CODES :
M 54HC X XX F 1 R
M 74 HC XX XM 1R
M 74HC X XX B1R
M 74H CXX XC 1R
The M54/74HC563 and M54HC573 are high speed
CMOS OCTAL LATCH WITH 3-STATE OUTPUTS
fabricated with in silicon gate C2MOS technology.
These ICs archive the high speed operation similar
to equivalent LSTTL while maintaning the CMOS
low power dissipation.
of D input data. While the OE input is at low level,
the eight outputs will be in a normal logic state (high
or low logic level) and while high level the outpts will
be in a high impedance state.
The application designer has a choise of
combination of inverting and non inverting outputs.
These 8 bit D-Type latches are controlled by a latch
enable input (LE) and a output enable input (OE).
While the LE input is held at a high level, the Q
outputs will follow the data input precisely or
inversely. When the LE is taken low, the Q outputs
will be latched precisely or inversely at the logic level
The three state output configuration and the wide
choise of outline make bus organized system
simple.
All inputs are equipped with protection circuits
against discharge and transient excess voltage.
PIN CONNECTION (top view)
HC563
HC573
HC563
HC573
October 1993
1/13
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