K6R1016C1D
TIMING WAVEFORM OF WRITE CYCLE(2) (OE =Low fixed)
PRELIMINARY
CMOS SRAM
Address
CS
UB, LB
WE
Data in
Data out
tAS(4)
High-Z
tWC
tAW
tCW(3)
tBW
tWR(5)
tWP1(2)
tWHZ(6)
tDW
tDH
Valid Data
tOW
High-Z
(10)
(9)
TIMING WAVEFORM OF WRITE CYCLE(3) (CS=Controlled)
Address
CS
UB, LB
WE
Data in
Data out
tAS(4)
High-Z
tLZ
High-Z
tWC
tAW
tCW(3)
tBW
tWR(5)
tWP(2)
tWHZ(6)
tDW
tDH
Valid Data
High-Z
High-Z(8)
-8-
Rev. 3.0
July 2004