ISP1562 데이터 시트보기 (PDF) - NXP Semiconductors.

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ISP1562

Hi-Speed USB PCI host controller

NXP Semiconductors. 

NXP Semiconductors

ISP1562

HS USB PCI host controller

7.7 Power-On Reset (POR)

Figure 3 shows a possible curve of VI(VAUX3V3) and VI(VREG3V3) with dips at t2 to t3 and t4

to t5. At t0, POR will start with 1. At t1, the detector passes through the trip level. Another

delay will be added before POR drops to 0 to ensure that the length of the generated

detector pulse, POR, is large enough to reset asynchronous flip-flops. If the dip is too

short (t4 to t5 < 11 µs), POR will not react and will stay LOW.

t0

t1

t2

t3

VPOR(trip) is typically 0.9 V.

Fig 3. Power-on reset

VI(VAUX3V3), VI(VREG3V3)

VPOR(trip)

t4 t5

POR

004aab194

7.8 Power supply

Figure 4 shows the ISP1562 power supply connection.

ISP1562_3

Product data sheet

Rev. 03 — 14 November 2008

© NXP B.V. 2008. All rights reserved.

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